Technical Program 2024

12:00 pm – 5:00 pm	Registration Open
12:30 pm – 5:00 pm	Tutorials and Workshops
6:00 pm – 9:00 pm	Sunday’s Reception and Panel CHIPS ACT, AI, Quantum Computing , and FPGAs Volker Sorger (University of Florida), David Andrews (University of Arkansas), Lesley Shannon (Simon Frazer University)

8:00 am – 8:45 am	Registration Open and Coffee/Tea (Breakfast on your own)
8:45 am – 9:00 am	Opening
9:00 am – 10:00 am	Keynote: Can Deep Learning Broaden the Participation of FPGA Designs? Speaker: Jason Cong, UCLA
10:00 am – 10:45 am	Poster Session A and Coffee/Tea Break
10:45 am – 12:15 pm	Session 1 – Applications Chair: Peipei Zhou (University of Pittsburgh)
	Bandwidth Efficient Homomorphic Encrypted Discrete Fourier Transform Acceleration on FPGA Zhihan Xu, Yang Yang (University of Southern California); Rajgopal Kannan (DEVCOM Army Research Lab); Viktor K. Prasanna (University of Southern California)
	High Throughput Massive MIMO Signal Decoding Using Multi-Level Tree Search on FPGAs Mohamed W Hassan, Hatem Ltaief, Suhaib A Fahmy (KAUST)
	PCQ: Parallel Compact Quantum Circuit Simulation (short paper) ★ Shuang Liang, Yuncheng Lu, Ce Guo, Wayne Luk, Paul H J Kelly (Imperial College London)
	PTME: A Regular Expression Matching Engine Based on Speculation and Enumerative Computation on FPGA (journal track) Sun, Mingqian (Southeast University – School of Cyber Science and Engineering) Xie, Guangwei (Fudan University – School of Computer Science); Zhang, Fan (National Digital Switching System Engineering and Technological Research Center); Guo, Wei (National Digital Switching System Engineering and Technological Research Center); Fan, Xitian (Shanghai Hongzhen Information Technology Co.,Ltd); Li, Tianyang (National Digital Switching System Engineering and Technological Research Center); Chen, Li (National Digital Switching System Engineering and Technological Research Center); Du, Jiayu (Purple Mountain Laboratories)
	DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP (journal track) Tamimi, Sajjad (Technical University of Darmstadt – Embedded Systems and Applications Group); Bernhardt, Arthur (Reutlingen University – Data Management Lab); Stock, Florian (Technical University of Darmstadt – Embedded Systems and Applications Group); Petrov, Ilia (Reutlingen University – Data Management Lab); Koch, Andreas (Technische Universität Darmstadt – Embedded Systems and Applications Group)
12:15 pm – 1:30 pm	Lunch
1:30 pm – 2:45 pm	Session 2 – Arithmetic Chair: Mark Shand (Waymo)
	HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory Abdul Rehman Tareen, Marius Meyer, Christian Plessl, Tobias Kenter (Paderborn University)
	Efficient 8-bit Matrix Multiplication on Intel Agilex-5 FPGAs ★ Sergey Gribok, Bogdan Pasca (Intel)
	Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs Endri Taka, Dimitrios Gourounas, Andreas Gerstlauer, Diana Marculescu (The University of Texas at Austin); Aman Arora (Arizona State University)
	DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration (journal track) Vakili, Shervin (Institut national de la recherche scientifique); Vaziri, Mobin (Polytechnique Montréal); Zarei, Amirhossein (Institut national de la recherche scientifique); Langlois, Pierre (Ecole Polytechnique de Montreal)
2:45 pm – 3:00 pm	Break
3:00 pm – 4:20 pm	Session 3 – Machine Learning I Chair: Cong “Callie” Hao (Georgia Institute of Technology)
	GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA Bingyi Zhang (University of Southern California); Rajgopal Kannan, Carl Busart (DEVCOM Army Research Lab); Viktor K. Prasanna (University of Southern California)
	PQA: Exploring the Potential of Product Quantization in DNN Hardware Acceleration (journal track) AbouElhamayed, Ahmed F. (Cornell University – Electrical and Computer Engineering); Cui, Angela (Cornell University); Fernandez-Marques, Javier (Flower Labs); Lane, Nicholas D. (University of Cambridge – Department of Computer Science and Technology); Abdelfattah, Mohamed S. (Cornell University – ECE)
	Accelerating ViT Inference on FPGA through Static and Dynamic Pruning Dhruv Parikh, Shouyi Li, Bingyi Zhang (University of Southern California); Rajgopal Kannan, Carl Busart (DEVCOM Army Research Lab); Viktor K Prasanna (University of Southern California)
	LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA (short paper) Shuxin Yang, Chenchen Ding (Southern University of Science and Technology, China); Mingqiang Huang (Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences); Kai Li, Zikun Wei, Hantao Huang, Hao Yu (Southern University of Science and Technology, China)
	LGBM2VHDL: Mapping of LightGBM Models to FPGA (short paper) Tomáš Martínek (Brno University of Technology); Jan Kořenek, Tomáš Čejka (CESNET, z. s. p. o.)
4:20 pm – 6:00 pm	Break
6:00 pm – 8:00 pm	Banquet, Demo Night, and Ph.D. Forum

8:00 am – 9:00 am	Registration Open and Coffee/Tea (Breakfast on your own)
9:00 am – 10:00 am	Keynote: Pets vs Cattle: Heterogeneous Systems in the 21st Century. Miriam Leeser (Northeastern University)
10:00 am – 10:45 am	Poster Session B and Coffee/Tea Break
10:45 am – 12:15 pm	Session 4 – Compilation & CAD Tool Chair: Jason Anderson (University of Toronto)
	Toward FPGA Intellectual Property (IP) Encryption from Netlist to Bitstream (journal track) Hutchings, Daniel; Taylor, Adam; Goeders, Jeff (Brigham Young University)
	LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization Rishov Sarkar, Rachel Paul, Cong (Callie) Hao (Georgia Institute of Technology)
	A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs ★ Zhili Xiong, Rachel Selina Rajarathnam, David Z. Pan (The University of Texas at Austin)
	Synthesis of LUT Networks for Random-Looking Dense Functions with Don’t Cares – Towards Efficient FPGA Implementation of DNN (short paper) ★ Yukio Miyasaka, Alan Mishchenko (UC Berkeley); Nicholas Fraser (AMD); John Wawrzynek (UC Berkeley)
	A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints (short paper) Qin Luo, Xinshi Zang, Qijing WANG (The Chinese University of Hong Kong); Fangzhou Wang (Cadence Design Systems); Evangeline F.Y. Young (The Chinese University of Hong Kong); Martin D.F. Wong (Hong Kong Captist University)
11:35 pm – 12:15 pm
12:15 pm – 1:30 pm	Lunch
1:30 pm – 2:50 pm	Session 5 – Architecture and CGRA Chair: Suhaib Fahmy (King Abdullah University of Science and Technology)
	HardCilk: Cilk-like Task Parallelism for FPGAs ★ Mohamed Mahfouz Shahawy, Canberk Sönmez, Cemalettin Cem Belentepe, Paolo Ienne (EPFL)
	Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams Rami Beidas, Jason H. Anderson (University of Toronto)
	MPC-Wrapper: Fully Harnessing the Potential of Samsung Aquabolt-XL HBM2-PIM on FPGAs Jinwoo Choi, Yeonan Ha, Hanna Cha, Seil Lee, Sungchul Lee (Yonsei University); Jounghoo Lee (Yonsei University / MangoBoost); Shin-haeng Kang (Samsung Electronics); Bongjun Kim, Hanwoong Jung (Samsung Advanced Institute of Technology); Hanjun Kim, Youngsok Kim (Yonsei University)
	FINESSD: Near-Storage Feature Selection with Mutual Information for Resource-Limited FPGAs Nikolaos Kyparissas, Gavin Brown, Mikel Lujan (The University of Manchester)
2:50 pm – 3:00 pm	Coffee Break
3:00 pm – 4:20 pm	Session 6 – Machine Learning 2 Chair: Mohamed Abdelfattah (Cornell University)
	Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference (journal track) Chen, Hongzheng (Cornell University); Zhang, Jiahao (Tsinghua University); Du, Yixiao (Cornell University); Xiang, Shaojie (Cornell University); Yue, Zichao (Cornell University); Zhang, Niansong (Cornell University); Cai, Yaohui (Cornell University); Zhang, Zhiru (Cornell University)
	SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction Petros Toupas (Imperial College London, UK – Information Technologies Institute (ITI)/CERTH, GR); Zhewen Yu, Christos-Savvas Bouganis (Imperial College London, UK); Dimitrios Tzovaras (Information Technologies Institute (ITI)/CERTH, GR)
	HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures (journal track) Zhao, Chenfeng (Washington University in St Louis, Computer Science & Engineering Department); Faber, Clayton J. (Washington University in St Louis – Computer Science & Engineering); Chamberlain, Roger D (Washington University – Computer Science and Engineering); Zhang, Xuan (Northeastern University)
	MRH-GCN: A Novel and Efficient GCN Accelerator for Multi-Relation Heterogeneous Graph (short paper) Wenlu Peng, Jianjun Chen, Wenjin Huang (Sun Yat-sen University); Yihua Huang (Sun-Yat-sen University)
	A Novel FPGA Accelerator of R(2+1) D (short paper) Dehao Xiang, Chenyang Li, Wenjin Huang (Sun Yat-sen University); Yihua Huang (Sun-Yat-Sen University)
4:20 pm – 5:00 pm	Closing and Award Ceremony

FCCM 2024 Program

Sunday (May 5) and Wednesday (May 8): Workshops and Tutorials

Sunday – May 5

Monday – May 6

Tuesday – May 7