FCCM 2023 Preliminary Program
*All times shown in the Pacific Time Zone (UTC-8)
Monday (May 8) and Thursday (May 11): Workshops and Tutorials
Tuesday – May 9
โ indicates best paper candidate
Open Research Objects (ORO)
Research Objects Reviewed (ROR) 
Results Reproduced (ROR-R) 
| 8:00 am – 8:45 am | Light Breakfast and Registration |
| 8:45 am – 9:00 am | Opening |
| 9:00 am – 10:00 am |
Keynote: The Programmable Imperative of Networking: Past and Future Speaker: Mike Fitton, Intel Chair: Viktor Prasanna |
| 10:15 am – 11:30 am |
Session 1 – High-Level Synthesis Chair: Ron Sass |
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LightningSim: Fast and Accurate Trace-Based Simulation for High-Level Synthesis โ
Rishov Sarkar and Cong Hao (Georgia Institute of Technology) |
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PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs Moazin Khatti and Xingyu Tian (Simon Fraser University); Yuze Chi, Licheng Guo, and Jason Cong (UCLA); Zhenman Fang (Simon Fraser University) |
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SCCL: An open-source SystemC to RTL translator Zhuanhao Wu (University of Waterloo); Maya Gokhale (Lawrence Livermore National Laboratory); Scott Lloyd (Brigham Young University); Hiren Patel (University of Waterloo) |
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Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs (short paper) Xiaochen Hao (Peking University); Hongbo Rong (Intel Labs); Mingzhe Zhang (Tsinghua University); Ce Sun (University of Science and Technology of China); Zhuofu Tao (University of California, Los Angeles); Yu Zhang (University of Science and Technology of China); Lei He (University of California, Los Angeles); Eric Petit (Intel); Wenguang Chen (Tsinghua University); Yun Liang (Peking University) |
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| 11:30 am – 12:00 pm | Poster Session A (virtual) |
| 12:00 pm – 1:30 pm | Lunch |
| 1:30 pm – 2:45 pm |
Session 2 – Architecture and CAD Chair: Kia Bazargan |
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Placement Optimization for NoC-Enhanced FPGAs โ
Srivatsan Srinivasan, Andrew Boutros, Fatemehsadat Mahmoudi, and Vaughn Betz (University of Toronto) |
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BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs Yuzong Chen and Mohamed Abdelfattah (Cornell University) |
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A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems โ
Andrew David Gunter and Steven Wilton (University of British Columbia) |
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CXL over Ethernet: A Novel FPGA-based Memory Disaggregation Design in Data Centers (short paper) Chenjiu Wang (SKLP, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences); Ke He (unaffiliated); Ruiqi Fan (SKLP, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences); Xiaonan Wang (WUXI Institute of Interconnect Technology); Wei Wang (unaffiliated); Qinfen Hao (SKLP, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences) |
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| 2:45 pm – 3:00 pm | Break |
| 3:00 pm – 4:15 pm |
Session 3 – Applications/ML Chair: Zhenman Fang |
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Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-integer Geometric Programming Yuhao Ding, Jiajun Wu, and Yizhao Gao (The University of Hong Kong); Maolin Wang (AI Chip Center for Emerging Smart Systems); Hayden So (The University of Hong Kong) |
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MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources Jiajun Wu, Jiajun Zhou, Yizhao Gao, Yuhao Ding, Ngai Wong, and Hayden So (The University of Hong Kong) |
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Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures Alireza Khataei, Gaurav Singh, and Kia Bazargan (University of Minnesota) |
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Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform (short paper) Pengzhou He, Tianyou Bao, Yazheng Tu, and Jiafeng Xie (Villanova University) |
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| 4:15 pm – 4:45 pm | Poster Session B (in person) |
| 4:45 pm – 6:00 pm | Break |
| 6:00 pm – 9:00 pm | Reception and Demo night |
Wednesday – May 10
| 8:00 am – 8:45 am | Light Breakfast and Registration |
| 9:00 am – 10:00 am |
Keynote: Bitstream Design Abstraction to Build Reconfigurable Machines and Applications Speaker: Prasanna Sundararajan Principal Architect, Microsoft Azure Chair: Wayne Luk, Imperial College London |
| 10:15 am – 11:15 am | Panel: Large Language Model (LLM) inference on FPGAs, GPUs, etc. |
| 11:15 am – 11:30 am | Break |
| 11:30 am – 12:00 pm | PhD Forum Posters (in person) |
| 12:00 pm – 1:30 pm | Lunch |
| 1:30 pm – 2:45 pm |
Session 4 – Applications/ML Chair: Mohamed Abdelfattah |
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ATHEENA: A Toolflow for Hardware Early-Exit Network Automation โ
Benjamin Biggs, George A. Constantinides, and Christos-Savvas Bouganis (Imperial College London, UK) |
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Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, and Dinesh Gaitonde (AMD) |
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HARFLOW3D: A latency-oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices Petros Toupas (Imperial College London, Information Technologies Institute at CERTH); Alexander Montgomerie-Corcoran (Imperial College London); Dimitrios Tzovaras (Information Technologies Institute at CERTH); Christos-Savvas Bouganis (Imperial College London, UK) |
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Power2Picture: Using Generative CNNs for Input Recovery of Neural Network Accelerators through Power Side-Channels on FPGAs Lukas Huegle, Martin Gotthard, Vincent Meyers, Jonas Krautter, Dennis R. E. Gnad, and Mehdi B. Tahoori (Karlsruhe Institute of Technology (KIT)) |
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| 2:45 pm – 3:00 pm | Break |
| 3:00 pm – 4:15 pm |
Session 5 – Applications Chair: Gabriel Weisz |
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Computing and Compressing Electron Repulsion Integrals on FPGAs Xin Wu, Tobias Kenter, Robert Schade, Thomas D. Kรผhne, and Christian Plessl (Paderborn University) |
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Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform Yuying ZHANG, Sathi Sarveswara Reddy, and Zili KOU (Hong Kong University of Science and Technology); Sharad Sinha (Indian Institute of Technology Goa); Wei ZHANG (Hong Kong University of Science and Technology) |
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SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms Alec Lu and Zhenman Fang (Simon Fraser University) |
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DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference (short paper) Hanqiu Chen and Cong Hao (Georgia Institute of Technology) |
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| 4:15 pm – 4:30 pm | Closing and Award Ceremony |