Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis |
T. Havinga; X. Jiao; W. Liu; I. Moerman |
Runtime Memory Disambiguation for Hybrid-Scheduled High-Level Synthesis |
R. Szafarczyk; S. Nabi; W. Vanderbauwhede |
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors |
Y. Gao; C. Keilbart; M. Chua; E. Matthews; S. Wilton; L. Shannon |
Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs |
F. Kono; N. Nakasato; M. Nakata |
ReLoDAQ: Resource-Efficient, Low Overhead 200 Gbit/s Data Acquisition System for 6G Prototyping |
C. Karle; M. Neu; J. Pfau; J. Sperling; J. Becker |
b8c: SpMV accelerator implementation leveraging high memory bandwidth |
J. Oliver; C. Álvarez; T. Cervero; X. Martorell; J. Davis; E. Ayguadé |
Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays |
M. Kabir; J. Hollis; A. Panahi; J. Bakos; M. Huang; D. Andrews |
HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks |
G. Yang; J. Lei; Z. Fang; Y. Li; J. Zhang; W. Xie |
Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management |
A. Filgueras; M. Vidal; D. Jiménez-González; C. Álvarez; X. Martorell |
A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing |
A. Drewes; V. Burtsev; B. Gurumurthy; M. Wilhelm; D. Broneske; G. Saake; T. Pionteck |
Efficient implementation of a Genetic Algorithm for the Capacitated Vehicle Routing Problem on a High-Performance FPGA |
M. Heer; J. Quevedo; M. Abdelatti; R. Sendag; M. Sodhi |
Decision Forest Training Accelerator Based on Binary Feature Decomposition |
T. Van Chu; Y. Mizutani; Y. Nagahara; S. Kumazawa; K. Kawamura; J. Yu; M. Motomura |
Accelerating Graph Analytics with oneAPI and Intel FPGAs |
J. Bickerstaff; L. Kljucaric; A. George |
FEASTS: Feature Extraction Accelerator for Streaming Time Series |
P. Yuvaraj; A. Kalantar; E. Keogh; P. Brisk |
PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design |
B. Peng; S. Sun; Y. Dai |
Scalable Quantum Error Correction for Surface Codes using FPGA |
N. Liyanage; Y. Wu; A. Deters; L. Zhong |
Clustering Classification on FPGAs for Neuromorphic Feature Extraction |
L. Kljucaric; D. George |
UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization |
Y. Dai; Y. Qiu; Q. Zhu; J. Li; W. Yin; L. Wang |