FCCM 2022 Workshops & Tutorials
Tentative Workshop and Tutorial Schedule
| All times are shown in Eastern Daylight Time (UTC-4) Links will be accessed through the virtual platform. |
| Date | Time | Type | Name | Organizer | Location |
|---|---|---|---|---|---|
| May 15 | 12:00pm - 4:00pm | Tutorial | T0: Introduction to Vitis AI development Tools Flow | Naveen Purushotham, AMD/Xilinx |
Zoom |
| May 15 | 12:00pm - 3:00pm | Tutorial | T1: OpenFPGA: Create your own FPGA with open-source tools | Nanditha Rao, Aman Arora, Xifan Tang, and Pierre-Emmanuel Gaillardon OSFPGA Foundation |
Zoom |
| May 15 | 4:00pm - 6:00pm | Tutorial | T2: Hands-On Tutorial: Introduction to oneAPI with Intel FPGAs | Ogheneuriri Oderhohwo, Intel |
Room 225 + Teams |
| May 18 | 9:00am - 12:00pm | Workshop | W0: First Workshop on Formal Methods In High-Level Synthesis | John P Wickerson (Imperial College London) and Lana Josipović (ETH) | Room 225 + Zoom |
| May 18 | 9:00am - 11:00am | Tutorial | T3: TAPA: High-Performance Customization-Friendly HLS Framework | Licheng Guo (UCLA) and Yuze Chi (Google) | Room 215 + Zoom |
| May 18 | 11:15am - 2:15pm | Workshop | W1: Workshop on Security for Custom Computing Machines | Dustin Richmond (UW), Ryan Kastner (UCSD), Jeff Goeders (BYU), and Mirjana Stojilovic (EPFL) | Zoom |
| May 18 | 11:15am - 2:15pm (including lunch break) |
Tutorial | T4: Recent Developments in Hardware Description Languages | Oron Port (Cornell University & DFiant Inc.) and Schuyler Eldridge (SiFive) | Room 215 + Zoom |
| May 18 | 1:00pm - 4:30pm | Tutorial | T5: CFU-Playground: Build Your Own Custom TinyML Processor | Shvetank Prakash, Colby Banbury, Vijay Janapa Reddi (Harvard) and Tim Callahan(Google) | Room 225 + Zoom |
| May 18 | 2:30pm - 4:30pm | Tutorial | T6: Nios V: RISC-V Based Processors for Intel FPGAs | Shreya Mehrotra, Intel |
Room 215 + Teams |
Workshop and Tutorial Details
T0: Introduction to Vitis AI development Tools Flow
Website: https://www.xilinx.com/support/university/workshops/schedule.html
T1: OpenFPGA: Create Your Own FPGA with Open-Source Tools
Abstract: This workshop will introduce the participants to OpenFPGA and showcase its capabilities and features through live demos. It will also provide them with hands-on training on how to use the OpenFPGA framework. It is targeted toward any FPGA enthusiasts and researchers who are interested in exploring novel FPGA architectures and/or fabricating their own custom FPGAs.
Website: https://osfpga.org/openfpga-create-your-own-fpga-with-open-source-tools/
More details can be found here
T2: Hands-On Tutorial: Introduction to oneAPI with Intel FPGAs
Abstract: oneAPI product delivers a unified programming model to simplify development across diverse architectures. Guaranteeing; Common developer experience across Scalar, Vector, Matrix and Spatial architectures; An uncompromised native high-level language performance, and Industry standardization and open specification.
Website: https://www.intel.com/content/www/us/en/developer/tools/oneapi/fpga.html#gs.wmsbqi
W0: First Workshop on Formal Methods In High-Level Synthesis
Website: https://flashlight-workshop.github.io/
W1: Workshop on Security for Custom Computing Machines
Abstract: Hardware security is an important design consideration. Recent events have raised awareness of security in general-purpose processors. As experts we must consider: What are the equivalents for reconfigurable architectures and custom computing machines? How do we defend against threats that exist today? How do we design our systems to defend against future threats? This is increasingly important as we deploy customized hardware at unprecedented scales.
This workshop is an opportunity to discuss security research and publicize our field at a top-tier FPGA conference. Our goal is to increase the awareness of ongoing research in this area, develop new collaborations, and share research progress. It will be organized as three separate lightning sessions. Each session will have a mini-keynote, a series of 5-minute pre-recorded lightning talks, and finally a Q&A period. We invite all people interested in security of custom computing machines to participate.
Website: /workshop-tutorial-2022/sccm
T4: Recent Developments in Hardware Description Languages
Schedule: more details can be found here.
T5: CFU-Playground: Build Your Own Custom TinyML Processor
Website: https://google.github.io/CFU-Playground/
T6: Nios V: RISC-V Based Processors for Intel FPGAs
Abstract: Nios® V soft processors are based on the RISC-V Instruction Set Architecture. In this session, we will provide an overview of the first processor in the Nios V series, the Nios V/m. We will also talk about the hardware and software development flows using Nios V. Finally, you’ll learn about the growing Nios V ecosystem that gives you access to your favorite compilers, debuggers and operating systems.
Website: https://www.intel.com/content/www/us/en/products/details/fpga/nios-processor/v.html