All times shown in Eastern Daylight Time (UTC-4)
Links will be emailed to registrants.

Main Program

Monday, May 10th

8:30 - 8:45 Opening
8:45 - 9:45 Session 1: FPGA CAD

Session Chair: Kia Bazargan

XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion
Matthew Hofmann, Zhiyao Tang, Jonathan Orgill, Jonathan Nelson, David Glanzman, Brent Nelson and Andre Dehon

A Safari through FPGA-based Neural Network Compilation and Design Automation Flows
Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer and Jürgen Teich

Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs
Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk and Steve Wilton
9:45 - 10:30 Poster Session 1
10:30 - 11:30 Session 2: Machine Learning 1 (Inference and Time-Series Prediction)

Session Chair: Miaoqing Huang

BoostGCN: A Framework for Optimizing GCN Inference on FPGA
Bingyi Zhang, Rajgopal Kannan and Viktor Prasanna

FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction
Amin Kalantar, Zachary Zimmerman and Philip Brisk

HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K.H. So and Kurt Keutzer
11:30 - 12:15 Keynote 1 (Maya Gokhale): FPGAs in High Performance Computing

Session Chair: Greg Stitt
12:15 - 13:30 Break for Lunch
13:30 - 14:30 Session 3: Applications 1 (Scientific Computing and Robotics)

Session Chair: He Li

GAME: Gaussian Mixture Model Mapping and Navigation Engine on Embedded FPGA
Yuanfan Xu, Zhaoliang Zhang, Jincheng Yu, Jianfei Cao, Haolin Dong, Zhengfeng Huang, Yu Wang and Huazhong Yang

Systematically migrating an operational microphysics parameterisation to FPGA technology
James Targett, Michael Lange, Olivier Marsden and Wayne Luk

Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design
Francesco Sgherzi, Alberto Parravicini, Marco Siracusa and Marco Santambrogio
14:30 - 15:40 Poster Session 2
15:40 - 17:00 Session 4: Architecture

Session Chair: Skand Hurkat

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs
Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi Iyer and Reetuparna Das

Benchmarking Optane DC Persistent Memory Modules on FPGAs
Jialiang Zhang, Nicholas Beckwith and Jing Li

FANS: FPGA Accelerated Near-Storage Sorting Solution
Weikang Qiao, Jihun Oh, Licheng Guo, Mau-Chung Frank Chang and Jason Cong

Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs
Frederick Tombs, Alireza Mellat and Nachiket Kapre
17:00 - 18:00 Break
18:00 Demo Night

Session Chair: Gabriel Weisz

Tuesday, May 11th

8:30 - 9:40 Session 5: Applications 2 (Medical, Biology, Physics)

Session Chair: John Wickerson

HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection (best paper candidate)
Gaspar Ribeiro, Nuno Neves, Sergio Santander-Jiménez and Aleksandar Ilic

The Importance of Being X-Drop: High Performance Genome Alignment on Reconfigurable Hardware (best paper candidate)
Alberto Zeni, Guido Walter Di Donato, Lorenzo Di Tucci, Marco Rabozzi and Marco Santambrogio

Upgrade of FPGA Range-Limited Molecular Dynamics to Handle Hundreds of Processors
Chunshu Wu, Tong Geng, Sahan Bandara, Chen Yang, Vipin Sachdeva, Woody Sherman and Martin Herbordt

FPGA-accelerated Iterative Reconstruction for Transmission Electron Tomography (short)
Linjun Qiao, Guojie Luo, Wentai Zhang and Ming Jiang
9:40 - 10:30 Poster Session 3
10:30 - 11:30 Session 6: Machine Learning 2 (CNNs)

Session Chair: Eriko Nurvitadhi

Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory
Chao Jiang, Dave Ojika, Bhavesh Patel and Herman Lam

unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation
Stylianos I. Venieris, Javier Fernandez-Marques and Nicholas Lane

ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA (short) (best paper candidate)
Pankaj Bhowmik, Md Jubaer Hossain Pantho, Joel Mandebi Mbongue and Christophe Bobda

3D-VNPU_A Flexible Accelerator for 2D/3D CNNs on FPGA (short)
Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng and Zhiyi Yu
11:30 - 12:00 Keynote 2 (Thomas Rondeau): DARPA’s FPGA Killer

Session Chair: Greg Stitt
12:00 - 13:15 Break for Lunch
13:15 - 14:35 Session 7: High-Level Synthesis

Session Chair: Dilip Vasudevan

Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs (best paper candidate)
Dillon Huff, Steve Dai and Pat Hanrahan

Probabilistic Scheduling in High-Level Synthesis
Jianyi Cheng, John Wickerson and George Constantinides

Extending High-Level Synthesis for Task-Parallel Programs
Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang and Jason Cong

HLS-Compatible, Embedded-Processor Stream Link (short)
Eric Micallef, Yuanlong Xiao and Andre Dehon

An Empirical Study of the Reliability of High-Level Synthesis Tools (short)
Yann Herklotz, Zewei Du, Nadesh Ramanathan and John Wickerson
14:35 - 15:15 Poster Session 4
15:15 - 16:15 Session 8: Security and Cloud Computing

Session Chair: Mirjana Stojilovic

Cloud FPGA Cartography using PCIe Contention
Shanquan Tian, Ilias Giechaskiel, Wenjie Xiong and Jakub Szefer

Trusted Configuration in Cloud FPGAs
Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, Ahmad-Reza Sadeghi and Nele Mentens

Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs (short) (best paper candidate)
Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel Holcomb, Russell Tessier and Jakub Szefer

Runtime Detection of Probing/Tampering on Interconnecting Buses (short)
Zhenyu Xu, Thomas Mauldin, Qing Yang and Tao Wei
16:15 Awards and Closing


Monday, May 10th

Title: FPGAs in High Performance Computing
Speaker: Maya Gokhale


The repurposing of FPGAs for computing was initiated three decades ago
as extreme compute accelerators to supercomputers. Today, FPGA
acceleration is commonplace in a diverse range of settings, from
extra-terrestrial to cloud. The US Department of Energy’s exascale
computer architectures will rely on extreme scale compute accelerators
to reach their 2 Exaflop target. In contrast to the early FPGA computing
vision and to the success of FPGAs in the cloud, the DOE exascale
machine accelerators will exclusively be GPUs. In this talk, I will
discuss factors determining HPC system architecture choices, challenges
facing FPGA computing in traditional HPC workloads, and novel
opportunities for FPGA acceleration in the expanding HPC arena.


Maya Gokhale is Distinguished Member of Technical Staff at the Lawrence
Livermore National Laboratory, USA. Her career spans research conducted
in academia, industry, and National Laboratories. Maya received a Ph.D.
in Computer Science from University of Pennsylvania. Her current
research interests include data intensive heterogeneous architectures
and reconfigurable computing. Maya is co-recipient of an R&D 100 award
for a C-to-FPGA compiler, co-recipient of four patents related to memory
architectures for embedded processors, reconfigurable computing
architectures, and cybersecurity, and co-author of more than one hundred
forty technical publications.
Maya is on the editorial board of the Proceedings of the IEEE and an
associate editor of IEEE Micro. She is a co-recipient of the National
Intelligence Community Award, is a member of Phi Beta Kappa, and is an
IEEE Fellow.

Tuesday, May 11th

Title: DARPA’s FPGA Killer
Speaker: Thomas Rondeau


FPGAs have many uses: embedded systems, glue logic on hardware devices, applications accelerators, and so on. In rough performance terms, an application will run a hundred times faster on an FPGA than in a general-purpose computer. But an ASIC could execute that application a thousand times faster. The problem is that ASIC development is slow, hard, and expensive (even more so than FPGA development). Moore’s Law has allowed us to cram more and more devices onto integrated circuits so that custom devices can now be fabricated with dozens or hundreds of components, including multicore CPUs, GPUs, accelerators, and memories. Such devices take years to implement and cost millions of dollars to fabricate – and the results is often inflexible and not able to adapt to changing requirements. DARPA’s Domain-Specific System on Chip program aims to improve the most significant aspects of SoC development and deployment so that complex SoCs targeted at multiple simultaneous applications can be implemented in months using automated, high-level software tools, and reconfigured or even reprogrammed at run-time to accommodate changing circumstances. Is this the end of the FPGA?


Dr. Tom Rondeau joined DARPA as a program manager in May 2016. His research interests include adaptive and reconfigurable radios, improving the development cycle for new signal-processing techniques, and creating general purpose electromagnetic systems.

Prior to joining DARPA, Dr. Rondeau was the maintainer and lead developer of the GNU Radio project and a consultant on signal processing and wireless communications. He worked as a visiting researcher with the University of Pennsylvania and as an Adjunct with the IDA Center for Communications Research in Princeton, NJ.

Dr. Rondeau holds a Ph.D. in electrical engineering from Virginia Tech and won the 2007 Outstanding Dissertation Award in math, science, and engineering from the Council of Graduate Schools for his work in artificial intelligence in wireless communications.