[kanshi]

Good work, congratulations. Few questions:
1. What’s the packet-rate performance (i.e. using small pkts such as 64B) that can be achieved from this work?
2. For both Tx and Rx, it is not clear how pkts are forwarded to ports. NIC will normally embody packet parser, classifier and lookup/exact-match/LPM/TCAM module for pkt lookup and forwarding, but those are missing from this design. Is this handled by the SW, i.e. determining which pkt goes to which queue, and directly mapping a given queue to a certain port?
3. The above question really is, that if this design is intended to be a ‘smart NIC’ or normal NIC. The former will offload several common network function stacks to FPGAs and free the CPU cores, and that’s the main point of these types of designs.
4. Is this NIC using customized SW driver? If so, two main issues. One, performance may be limited, but authors mentioned to use DPDK-based driver in the future work, so it will improve performance. Second, limited generalization capability.

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