FCCM 2026 Accepted Paper List ( * next to paper name indicates conditional accept with shepherding)
| ID | Format | Title | Authors |
|---|---|---|---|
| 11 | Long | ReFHE-NTT: Resource-Driven NTT FPGA Architecture for Fully Homomorphic Encryption | V. Guerrini, S. Giuseppe, A. Barenghi, D. Conficconi |
| 18 | Long | * LUT-LLM: Efficient Language Model Inference with Memory-based Computations on FPGAs | Z. He, S. Ye, R. Ma, Y. Wang, J. Cong |
| 27 | Long | AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Engines | D. Danopoulos, E. Lupi, C. Sun, S. Dittmeier, M. Kagan, V. Loncar, M. Pierini |
| 52 | Long | Trident: Efficient FPGA Acceleration of XMSS Tree in Post-Quantum Signature Scheme SLH-DSA | T. Bao, J. Ennis, K. Morozov, J. Xie |
| 55 | Long | A Robotics Middleware for FPGAs Supporting Dynamic Function Exchange and Streaming Data Distribution | A. Nowosad, C. Lienen, M. Platzner |
| 87 | Long | SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization | G. Li, Y. Cao, L. Ng, A. Charlton, Q. Wang, W. Punter, P. Papaphilippou, C. Guo, H. Fan, W. Luk, S. Amarasinghe, A. Brahmakshatriya |
| 88 | Long | Enabling Net-Level Global Vision in FPGA Routing via Precomputed Steiner Potential Fields | Y. Liu |
| 89 | Long | ReCoVLM: A Reconfigurable FPGA–GPU Co-Design for Edge Vision-Language Inference | J. Wang, Y. Xue, K. Zhuang, M. Sun, Q. Song |
| 94 | Long | * DiffRouter: A Differentiable Routing Framework for UltraScale FPGAs | X. Gao, Z. Xiong, Y. Wang, D. Pan |
| 108 | Long | Hardware stencil accelerator with periodic boundary conditions | D. Simon, O. Sentieys, S. Lefebvre |
| 111 | Long | EZCache: Easy Action-Enabled FPGA Caches for Non-Stalling Datapaths in SmartNICs and Beyond | A. Abdelsalam, V. Gondaliya, E. Hamed, P. Math, M. Gepigon, J. Landgraf, N. Gebara, B. Groza, D. Lee, A. Verma, A. Putnam |
| 131 | Long | ViM-Q: Scalable Algorithm-Hardware Co-Design for Vision Mamba Model Inference on FPGA | S. Lyu, Y. She, P. Hung, R. Cheung, W. Xu |
| 141 | Long | Adaptive AIE–PL Systems for Efficient End-to-End Pyramidal 3D Image Registration | S. GIUSEPPE, P. Galfano, C. Di Salvo, E. D’Arnese, D. Conficconi |
| 190 | Short | Δ2-PSUM: A Low-Latency Soft-Error-Resilient Binary Neural Network Inference Processor | S. Jeong, T. Kim |
| 199 | Long | * When Systolic Arrays Meet AI Engines: Architectural Constraints on AMD Versal ACAP | J. Kimko, J. Cong |
| 237 | Long | GraphLeap: Decoupling Graph Construction and Convolution for Vision GNN Acceleration on FPGA | A. Ramachandran, D. Parikh, V. Prasanna |
| 241 | Long | FHPSAC: FPGA-based High-Parallelism SAC Accelerator | J. Xu, W. Fan, X. Zhou, W. Cao, J. Chen, F. Zhang, F. Zhang, X. Yu |
| 247 | Short | * TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation with Emerging AI Formats | J. Wang, M. Nie, S. Lin, C. Shi, A. Li |
| 256 | Long | Enabling Context-Switchable Monolithic 3D FPGA Design Using Bistable Ferroelectric Inverters | F. Waqar, M. Chen, Z. He, Z. Wan, M. Shon, W. Huang, J. Cong, S. Yu |
| 257 | Long | ImageHD: Energy-Efficient On-Device Continual Learning of Visual Representations via Hyperdimensional Computing | J. Arockiaraj, D. Parikh, V. Prasanna |
| 273 | Long | FASTR: FPGA-based Acceleration of Hierarchical Foundation Models for SAR ATR | S. Wickramasinghe, C. Raghavendra, V. Prasanna |
| 286 | Long | HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference | C. Sun, Z. Que, B. Zadeh, Q. Liu, K. Alvarez, W. Luk, M. Spiropulu |
| 290 | Short | VSALUT: A Lightweight Low-Dimensional VSA Classifier for Efficient Inference on FPGA | N. Narkthong, X. Xu |
| 344 | Long | NetCilk: Extending Task-Level Parallelism Seamlessly Across FPGAs | M. Shahawy, C. Sonmez, P. Ienne |
| 349 | Long | PathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization | S. Shrivastava, L. Kurešević, A. Poupakis, C. Ravishankar, D. Gaitonde, S. Nikolić, M. Stojilović |
| 354 | Long | The Optimal, The Fast, and The Hybrid: Automatic Placement and Routing for AIE Arrays | H. Yan, J. Yen, R. Zhang, A. Boutros, V. Betz |
| 429 | Long | LegoMap: Optimization for High-Throughput Transformer Computing on AI Engine-Based FPGAs | H. Hu, H. Chang, D. Fang, Z. Wang, W. Li, R. Liang, B. Yuan, J. Hu |
| 455 | Short | AccelOrb: FPGA Acceleration of Orb v2 for Fast Molecular Dynamics | S. Kim, G. Park, J. Lim, F. Asim, J. Lee |
| 471 | Long | Déjà Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization | M. Liebster, A. Mohaghegh, A. Boutros |