[tuanla]

Hi,

Thank you for that geeky question.

SRL and Distributed RAM are operated as synchronous write and asynchronous read.
Therefore, similar with normal LUT operation, it is possible to create glitches in read mode since no clock edge is required to sync the output data.
In that case, if we detect LUTs are in alternative modes (SRL or Distributed RAM) then we will give them the worst case glitch score (LUT as a wide XOR).

Best wishes,
Tuan La

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