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Program

Sunday 29th April
14:30 - 16:00	FPGA Machine Learning Research in the Next Decade
16:30 - 18:00	Identifying Startup Opportunities Within your Research
19:30 - 21:30	FCCM 2018 Opening Reception (drinks and appetizers)
Monday 30th April - Day 1
07:45 - 08:45	Breakfast and Registration
08:45 - 09:00	Welcoming Remarks
09:00 - 10:05	Paper Session M1 : Computation and NoCs
10:05 - 11:10	Poster Session P1
11:10 - 12:15	Paper Session M2 : Cryptography, Compression, and Security
12:15 - 12:30	Announcements
12:30 - 14:00	Lunch
14:00 - 15:05	Paper Session M3 : Machine Learning
15:05 - 16:00	Poster Session P2
16:00 - 16:30	Paper Session M4 : Leveraging Platform Technology
18:30 - 21:00	Demo Night
Tuesday 1st May - Day 2
07:45 - 08:45	Breakfast and Registration
08:45 - 09:00	Announcements
09:00 - 10:10	Paper Session T1 : High Level Synthesis
10:10 - 11:15	Poster Session P3
11:15 - 12:15	Paper Session T2 : FPGA CAD and Architectures
12:15 - 12:20	Announcements
12:20 - 14:00	Lunch
14:00 - 15:00	Paper Session T3 : Memory
15:00 - 15:30	Break
15:30 - 16:30	Paper Session T4 : Applications
16:30 - 16:40	Closing Remarks and Best Paper Award

Demo Night

Each year we have an informal show-and-tell called Demo Night. This year it's Monday evening, April 30, 2018 at 18:30. Paper and poster authors and commercial vendors bring their FCCMs, hardware, gateware, slideware, software, tools, chips, and set up demos. Attendees circulate, enjoy the demos, and engage with the presenters while enjoying the food and drink at this stand-up and learn event. It's always informative for demoers and demoees, great networking, and lots of fun too.

Technical Program : Papers

Monday 30th April
07:45 - 08:45	Breakfast and Registration
08:45 - 09:00	Welcoming Remarks
09:00 - 10:05	Paper Session M1 : Computation and NoCs Chair: Paul Chow
09:00 - 09:20	Evaluating the performance efficiency of a soft- processor, variable-length, parallel-execution-unit architecture for FPGAs using the RISC-V ISA Eric Matthews, Zavier Aguila and Lesley Shannon
09:20 - 09:40	ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou and Jason Cong
09:40 - 10:00	Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs Siddhartha and Nachiket Kapre
10:00 - 10:05	A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip (short) Shivukumar B. Patil, Tianqi Liu and Russell Tessier
10:05 - 11:10	Poster Session P1
11:10 - 12:15	Paper Session M2 : Cryptography, Compression, and Security Chair: Andrew Schmidt
11:10 - 11:30	Improved Lightweight Implementations of CAESAR Authenticated Ciphers Farnoud Farahmand, William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps and Kris Gaj
11:30 - 11:50	High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang and Jason Cong
11:50 - 12:10	FPGA Side Channel Attacks without Physical Access Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sebastien Pillement, Daniel Holcomb and Russell Tessier
12:10 - 12:15	Inheriting Software Security Policies Within Hardware IP Components (short) Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho and Christophe Bobda
12:15 - 12:30	Announcements
12:30 - 14:00	Lunch
14:00 - 15:05	Paper Session M3 : Machine Learning Chair: Jason Cong
14:00 - 14:20	ReBNet: Residual Binarized Neural Network Mohammad Ghasemzadeh, Mohammad Samragh and Farinaz Koushanfar
14:20 - 14:40	FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks Amir Yazdanbakhsh, Michael Brzozowski, Behnam Khaleghi, Soroush Ghodrati, Kambiz Samadi, Hadi Esmaeilzadeh and Nam Sung Kim
14:40 - 15:00	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit Mishra, Martin Margala and Kevin Nealis
15:00 - 15:05	FPDeep: Acceleration and Load Balancing of CNN Training on FPGA Clusters (short) Tong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rui Xu, Rushi Patel and Martin Herbordt
15:05 - 16:00	Poster Session P2
16:00 - 16:30	Paper Session M4 : Leveraging Platform Technology Chair: Mike Wirthlin
16:00 - 16:20	Hot & Spicy: Improving Productivity with Python and HLS Sam Skalicky, Joshua Monson, Andrew Schmidt and Matthew French
16:20 - 16:25	Understanding Performance Differences of FPGAs and GPUs (short) Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu and Shaochong Zhang
16:25 - 16:30	High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex (short) Madison N Emas, Austin Baylis and Greg Stitt
18:30 - 21:00	Demo Night
Tuesday 1st May
08:45 - 09:00	Announcements
09:00 - 10:10	Paper Session T1 : High-Level Synthesis Chair: Jeff Goeders
09:00 - 09:20	Concurrency-Aware Thread Scheduling for High-Level Synthesis Nadesh Ramanathan, George Constantinides and John Wickerson
09:20 - 09:40	High-Level Synthesis of FPGA Circuits with Multiple Clock Domains Omar Ragheb and Jason Anderson
09:40 - 10:00	LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing Asif Islam and Nachiket Kapre
10:00 - 10:05	Latte: Locality Aware Transformation for High-Level Synthesis (short) Jason Cong, Peng Wei, Cody Hao Yu and Peipei Zhou
10:05 - 10:10	Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning (short) Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline Young and Zhiru Zhang
10:10 - 11:15	Poster Session P3
11:15 - 12:15	Paper Session T2 : FPGA CAD and Architectures Chair: James Davis
11:15 - 11:35	RapidWright: Enabling Custom Crafted Implementations for FPGAs Chris Lavin and Alireza Kaviani
11:35 - 11:55	Improving the Effectiveness of TMR Applications on FPGAs with an SEU-Aware Incremental Placement Technique Matthew Cannon, Andrew Keller and Michael Wirthlin
11:55 - 12:15	Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ Jeffrey Goeders, Tanner Gaskin and Brad Hutchings
12:15 - 12:20	Annoucements
12:20 - 14:00	Lunch
14:00 - 15:00	Paper Session T3 : Memory Chair: Jan Gray
14:00 - 14:20	HODS: Hardware Object Deserialization inside SSD Storage Dongyang Li, Fei Wu, Yang Wen, Qing Yang and Changsheng Xie
14:20 - 14:40	CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms Liang Feng, Sharad Sinha, Wei Zhang and Yun Liang
14:40 - 15:00	Microscope on Memory: MPSoC-enabled Computer Memory System Assessments Abhishek Jain, Scott Lloyd and Maya Gokhale
15:00 - 15:30	Break
15:30 - 16:30	Paper Session T4 : Applications Chair: John Lockwood
15:30 - 15:50	FPGA-based Real-time Super-Resolution System for Ultra High Definition Videos Ho Cheuk-Lun, Hanxian Huang, Ming Jiang, Yuanchao Bai and Guojie Luo
15:50 - 16:10	OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner and Christian Plessl
16:10 - 16:30	A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath Makoto Saitoh, Elsayed Abdellah, Thiem Van Chu, Susumu Mashimo and Kenji Kise
16:30 - 16:40	Closing Remarks and Best Paper Award

Technical Program : Posters

Monday 30th April
07:45 - 08:45	Breakfast and Registration
08:45 - 09:00	Welcoming Remarks
09:00 - 10:05	Paper Session M1 : Computation and NoCs
10:05 - 11:10	Poster Session P1
	A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip Shivukumar B. Patil, Tianqi Liu and Russell Tessier
	Inheriting Software Security Policies Within Hardware IP Components Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho and Christophe Bobda
	EM-Aware Memory Mapping Algorithms for SRAM Based FPGA Zhong Guan
	SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei and Tianhe Yu
	PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGA Jialiang Zhang and Jing Li
	NewGraph: Balanced Large-scale Graph Processing on FPGAs with Low Preprocessing Overheads Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang and John Wawrzynek
	Exploiting Box Expansion and Grid Partitioning for Parallel FPGA Routing Minghua Shen, Guojie Luo and Nong Xiao
	AccDNN: an IP-based DNN Generator for FPGAs Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-Mei Hwu and Deming Chen
	Reloc -- An Open-Sourced Vivado Workflow for Generating Relocatable End-User Configuration Tiles Björn Gottschall, Thomas Preußer and Akash Kumar
	From C to Fault-Tolerant FPGA-based Systems Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin and Oliver Diessel
	Automatic Interior I/O Elimination in Systolic Array Architecture Jason Cong and Jie Wang
11:10 - 12:15	Paper Session M2 : Cryptography, Compression, and Security
12:15 - 12:30	Announcements
12:30 - 14:00	Lunch
14:00 - 15:05	Paper Session M3 : Machine Learning
13:05 - 16:00	Poster Session P2
	FPDeep: Acceleration and Load Balancing of CNN Training on FPGA Clusters Tong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rui Xu, Rushi Patel and Martin Herbordt
	Understanding Performance Differences of FPGAs and GPUs Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu and Shaochong Zhang
	High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex Madison N Emas, Austin Baylis and Greg Stitt
	Wibheda: Framework for Data Dependency-aware Multi-constrained Hardware-Software Partitioning in FPGA-based SoCs for IoT Devices Deshya Wijesundera, Alok Prakash, Thilina Perera, Kalindu Herath and Thambipillai Srikanthan
	High-speed Regular Expression Matching with Pipelined Memory-based Automata Denis Matoušek, Jiří Matoušek and Jan Kořenek
	Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow Nele Mentens, Edoardo Charbon and Francesco Regazzoni
	A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media Abdul-Amir Yassine, Omar Ragheb, Yasmin Afsharnejad, Vaughn Betz and Paul Chow
	Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews and Marjan Asadinia
	Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA Sunwoong Kim and Rob Rutenbar
	High Performance Dynamic Communication on Reconfigurable Clusters Jiayi Sheng, Chen Yang and Martin Herbordt
	Performance Prediction for Large-scale Heterogeneous Platforms Ryota Yasudo, Ana Lucia Varbanescu, Jose Gabriel Figueiredo Coutinho, Wayne Luk and Hideharu Amano
16:00 - 16:30	Paper Session M4 : Leveraging Platform Technology
18:30 - 21:00	Demo Night
Tuesday 1st May
07:45 - 08:45	Breakfast and Registration
08:45 - 09:00	Announcements
09:00 - 10:10	Paper Session T1 : High-Level Synthesis
10:10 - 11:15	Poster Session P3
	Latte: Locality Aware Transformation for High-Level Synthesis Jason Cong, Peng Wei, Cody Hao Yu and Peipei Zhou
	Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline Young and Zhiru Zhang
	Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce Katayoun Neshatpour, Hosein Makrani, Avesta Sasan, Hassan Ghasemzadeh, Setareh Rafaitrad and Houman Homayoun
	Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials José Luis Imaña
	A PYNQ-based Framework for Rapid CNN Prototyping Erwei Wang, James J. Davis, and Peter Y. K. Cheung
	Automatic Offloading of Cluster Accelerators Ciro Ceissler, Ramon Nepomuceno, Marcio Pereira and Guido Araujo
	Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation Jieming Xu and Miriam Leeser
	Bridging the Gap Between Advanced Memory and Heterogeneous Architectures Abhi D.R., Ron Sass, Andrew Schmidt and Matthew French
	Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander Veidenbaum and Alexandru Nicolau
11:15 - 12:15	Paper Session T2 : FPGA CAD and Architectures
12:15 - 12:20	Announcements
12:20 - 14:00	Lunch
14:00 - 15:00	Paper Session T3 : Memory
15:00 - 15:30	Break
15:30 - 16:30	Paper Session T4 : Applications
16:30 - 16:40	Closing Remarks and Best Paper Award