FCCM 2006

The 14th IEEE International Symposium on
Field-Programmable Custom Computing Machines

April 24-26, 2006

Technical Programme : Papers

Monday, April 24, 2006
Paper Session 1 : Supercomputer Applications
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer
Gerald Morris, Richard Anderson, Viktor Prasanna
A Case Study in Porting a Production Scientific Supercomputing Application to a Reconfigurable Computer
Volodymyr Kindratenko, David Pointer
A Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers
Ronald Scrofano, Maya Gokhale, Frans Trouw, Viktor Prasanna
Poster Session 1
Paper Session 2 : Methodology and Tools
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
Chun Hok Ho, Philip Leong, Wayne Luk, Steve Wilton and Sergio Lopez-Buedo
Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions
David Lau, Orion Pritchard and Philippe Molson
Paper Session 3 : Data Generation and Processing
Efficient Hardware Generation of Random Variates with Arbitrary Distributions
David B. Thomas and Wayne Luk
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems
Zachary Baker and Viktor Prasanna
Automatic Sliding Window Operation Optimization for FPGA-Based Computing Boards
Haiqian Yu and Miriam Leeser
Poster Session 2
Paper Session 4 : Hybrid Systems
Enabling a Uniform Programming Model Across the Software/Hardware Boundary
Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp and David Andrews
A Type Architecture for Hybrid Micro-Parallel Computers
Benjamin Ylvisaker, Brian Van Essen and Carl Ebeling
Tuesday, April 25, 2006
Paper Session 5 : Multi-Processor/Multi-Threaded Systems
A Scalable FPGA-based Multiprocessor
Arun Patel, Manuel Saldaa, Christopher Comis, Paul Chow, Christopher A. Madill and Rgis Poms
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
Charles Cathey, Jason Bakos and Duncan Buell
A Multithreaded Soft Processor for SoPC Area Reduction
Blair Fort, Davor Capalija, Zvonko G. Vranesic and Stephen D. Brown
Poster Session 3
Paper Session 6 : Graph Algorithms
GraphStep: A System Architecture for Sparse-Graph Algorithms
Michael deLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas Uribe, Thomas Knight and Andre DeHon
Hardware/Software Codesign for All-Pairs Shortest-Paths on a Reconfigurable Supercomputer
Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg and P. Sadayappan
Paper Session 7 : Power and Energy Optimization
A Field Programmable RFID Tag and Associated Design Flow
Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shenchih Tung, Ralph Sprang, Josh Fazekas, James T. Cain and Marlin H. Mickle
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
Robert Dimond, Oskar Mencer and Wayne Luk
Power Visualization, Analysis, and Optimization Tools for FPGAs
Matthew French, Li Wang and Michael Wirthlin
Poster Session 4
Paper Session 8 : Network Technology
Systematic Characterization of Programmable Packet Processing Pipelines
Michael Attig and Gordon Brebner
Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks
Nachiket Kapre, Nikil Mehta, Michael deLorimier, Raphael Rubin, Henry Barnor, Michael Wilson, Michael Wrighton and Andre DeHon
Wednesday, April 26, 2006
Paper Session 9 : Biomedical and Cryptographic Applications
Single Pass Approximate String Matching on FPGAs
Martin Herbordt, Tom VanCourt, Yongfeng Gu, Josh Model and Bharat Sukhwani
An FPGA Solution for Radiation Dose Calculation
Kevin Whitton, X. Sharon Hu and Cedric Yu
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
Andrey Bogdanov, Marius C. Mertens, Christof Paar, Jan Pelzl and Andy Rupp
Poster Session 3
Paper Session 10 : Arithmetic
Advanced Components in the Variable Precision Floating-Point Library
Xiaojun Wang, Sherman Braganza and Miriam Leeser
Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components
Robert Strzodka and Dominik Gddeke