FCCM 2005

The 13th IEEE International Symposium on
Field-Programmable Custom Computing Machines

April 17-20, 2005

Technical Programme : Papers

Monday, April 18, 2005
Paper Session 1 : Applications I
Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs
Zachary K. Baker, Viktor K. Prasanna
A Novel 2D Filter Design Methodology for Heterogeneous Devices
Christos-Savvas Bouganis, George A. Constantinides, Peter Y.K. Cheung
Prototyping Architectural Support for Program Rollback Using FPGAs
Radu Teodorescu, Josep Torrellas
Poster Session 1
Paper Session 2 : Architecture
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
Zion Kwok, Steven J.E. Wilton
Handling Different Computational Granularity by a Reconfigurable IC featuring Embedded FPGAa and a Network-on-Chip
Francesco Lertora, Michele Borgatti
Paper Session 3 : Tools I
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Roman Lysecky, Frank Vahid, Sheldon X.-D. Tan
Simplifying the Integration of Processing Elements in Computing Systems using a Programmable Controller
Lesley Shannon, Paul Chow
Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures
Pedro C. Diniz
Poster Session 2
Paper Session 4 : Graphics
FPGA Particle Graphics Hardware
John S. Beeckler, Warren J. Gross
Reconfigurable Designs for Radiosity
Paul Baker, Tim Todman, Henry Styles, Wayne Luk
Tuesday, April 19, 2005
Paper Session 5 : Applications II
Hardware Factorization Based on Elliptic Curve Method
Martin Simka, Jan Pelzl, Thorsten Kleinjung, Milos Drutarovsky, Viktor Fischer, Christof Paar
Metropolitan Road Traffic Simulation on FPGAs
Justin L. Tripp, Henning S. Mortveit, Anders A. Hansson, Maya Gokhale
Time Domain Numerical Simulation for Transient Wave Equations on Reconfigurable Coprocessor Platform
Chuan He, Wei Zhao, Mi Lu
Poster Session 3
Paper Session 6 : Run Time
COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors
Jingzhao Ou, Viktor K. Prasanna
An Execution Environment for Reconfigurable Computing
W. Fu, K. Compton
Paper Session 7 : Arithmetic
Higher Radix Floating-Point Representations for FPGA-Based Arithmetic
Bryan Catanzaro, Brent Nelson
An Analysis of the Double-Precision Floating-Point FFT on FPGAs
K. Scott Hemmert, Keith Underwood
A Comparision of Floating Point and Logarithmic Number Systems for FPGAs
Michael Haselman, Michael Beauchamp, Aaron Wood, Scott Hauck, Keith Underwood, K. Scott Hemmert
Poster Session 4
Paper Session 8 : Device Architecture
Terrestrial-Based Radiation: A Cautionary Tale
Heather Quinn, Paul Graham
Automating the Layout of Reconfigurable Subsystems using Circuit Generators
Shawn Phillips, Scott Hauck
Wednesday, April 20, 2005
Paper Session 9 : Networking
Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network
Young H. Cho, William H. Mangione-Smith
A Framework For Rule Processing in Reconfigurable Network Systems
Michael E. Attig, John W. Lockwood
A Signature Match Processor Architecture for Network Intrusion Detection
Janardham Singaraju, Long Bu, John A. Chandy
Poster Session 3
Paper Session 10 : Tools II
Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation
Jose Gabriel F. Coutinho, Jun Jiang, Wayne Luk
Modeling and FPGA Implementation of Applications using Parameterized Process Networks with Non-Static Parameters
Hristo Nikolov, Todor Stefanov, Ed Deprettere