FCCM 2004

The 12th IEEE International Symposium on
Field-Programmable Custom Computing Machines

April 20-23, 2004

Technical Programme : Papers

Wednesday, April 21, 2004
Paper Session 1 : Architecture
Time-Critical Software Deceleration in an FCCM
P. James-Roxby, G. Brebner, D. Bemmann
Design Patterns for Reconfigurable Computing
A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi, M. Vanier, M. Wrighton
Virtual Memory Window for Portable Reconfigurable Cryptography Coprocessor
M. Vuletic, L. Pozzi and P. Ienne
Poster Session 1
Paper Session 2 : Tools I
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs
G. Mittal, D. Zaretsky, X. Tang, P. Banerjee
PyGen: A MATLAB/Simulink based Tool for Parameterized and Energy
J. Ou and V. Prasanna
Paper Session 3 : Arithmetic I
Automated Least-Significant Bit Datapath Optimization for FPGAs
M.L. Chang and S. Hauck
An Arithmetic Library and its Application to the N-body Problem
K.H. Tsoi, C.H. Ho, H.C. Yeung and P.H.W. Leong
Unifying Bit-width Optimisation for Fixed-point and Floating-point Designs
A. Gaffar, O. Mencer, W. Luk and P.Y.K. Cheung
Poster Session 2
Paper Session 4 : Communications Applications
A Dynamically Reconfigurable, Power-Efficient Turbo Decoder
J. Liang, R. Tessier and D. Goeckel
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
D-U Lee, W. Luk, C. Wang, C. Jones, M. Smith, J. Villasenor
Thursday, April 22, 2004
Paper Session 5 : Networking I
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
R. Krishnamurthy, S. Yalamanchili, K. Schwan, R. West
Deep Packet Filter with Dedicated Logic and Read Only Memories
Y. Cho and W. Mangione-Smith
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Z. Baker and V. Prasanna
Poster Session 3
Paper Session 6 : Applications I
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
M. Leeser, S. Miller and H. Yu
FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method
J. Durbano, F. Ortiz, J. Humphrey, P. Curt, D. Prather
Paper Session 7 : Tools II
Register Binding for FPGAs with Embedded Memory
H. Al Atat and I. Ouaiss
Defect and Fault Tolerance for Reconfigurable Molecular Computing
M. Tahoori and S. Mitra
Communications Scheduling for Concurrent Processes on Reconfigurable Computers
M. Gokhale, C. Ahrens, J. Frigo, C. Wolinski
Poster Session 4
Paper Session 8 : Applications II
Reconfigurable Molecular Dynamics Simulator
N. Azizi, I. Kuon, A. Egier, A. Darabiha and P. Chow
Accelerating Seismic Migration Using FPGA-based Coprocessor Platform
C. He, M. Lu, C. Sun

Friday, April 23, 2004
Paper Session 9 : Arithmetic II
Closing the gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance
Keith D. Underwood and K. Scott Hemmert
FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit
C. Doss and R. Riley
On-Line IEEE Floating-Point Arithmetic for FPGAs
S. Krueger, P-M. Seidel
Poster Session 3
Paper Session 10 : Networking II
Scalable Multi-Pattern Matching on High-Speed Networks
C. Clark and D. Schimmel
Pre-decoded CAMs for Efficient and High-Speed NIDS Pattern Matching
Ioannis Sourdis and Dionisios Pnevmatikatos