FCCM 1998

The 6th IEEE International Symposium on
Field-Programmable Custom Computing Machines

April 14-17, 1998

Technical Programme : Papers

Wednesday, April 15, 1998
Paper Session 1 : Architectures I
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
T. Miyamori and K. Olukotun
Exploring Optimal Cost-Performance Designs for Raw Microprocessors
C.A. Moritz, D. Yeung, and A. Agarwal
The NAPA Adaptive Processing Architecture
C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale
Poster Session 1
Paper Session 2 : Special Purpose Systems
A Stream-Based Configurable Computing Radio Testbed
S. Swanchara, S. Harper, and P. Athanas
Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation
A. Dollas, E. Sotiriades, and A. Emmanonelides
Paper Session 3 : Architectures II
New FPGA Architecture for Bit-Serial Pipeline Datapath
A. Ohta, T. Isshiki, and H. Kunieda
Plastic Cell Architecture: Towards Reconfigurable Computing for General Purpose
K. Nagami, K. Oguri, T. Shiozawa, H. Ito, and R. Konishi
The Design and Implementation of a Context Switching FPGA
S.M. Scalera and J.R. Vazquez
Poster Session 2
Paper Session 4 : Applications I
A Run-Time Reconfigurable Engine for Image Interpolation
R. Hudson, D. Lehn and P. Athanas
Hardware/Software Integration in Solar Polarimetry
M. Shand and L. Moll
Thursday, April 16, 1998
Paper Session 5 : Compilers
An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems
A.A. Duncan, D.C. Hendry, P. Cray
Specifying and Compiling Applications for RaPiD
D. Cronquist, P. Franklin, S. Berg and C. Ebeling
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
M.B. Gokhale and J.M. Stone
Poster Session 3
Paper Session 6 : Tools for Run Time Reconfiguration
Configuration Compression for the Xilinx XC6200 FPGA
S. Hauck, Z. Li and E. Schwabe
Automating Production of Run-Time Reconfigurable Designs
N. Shirazi, W. Luk and P.Y.K. Cheung
Paper Session 7 : Module Generation
Object Oriented Circuit-Generators in Java
M. Chu, K. Sulimma, N. Weaver, A. DeHon, J. Wawrzynek
PAM-Blox: High Performance FPGA Design for Adaptive Computing
O. Mencer, M. Morf and M. J. Flynn
JHDL - An HDL for Reconfigurable Systems
P. Bellows and B. Hutchings
Poster Session 4
Paper Session 8 : Applications II
Accelerating Boolean Satisfiability with Configurable Hardware
P. Zhong, M. Martonosi, P. Ashar and S. Malik
Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability
A. Rashid, J. Leonard and W.H. Mangione-Smith
Friday, April 17, 1998
Paper Session 9 : Arithmetic
A Re-evaluation of the Practicality of Floating Point Operations on FPGAs
W. Ligon, S. McMillan, G. Monn, F. Stivers and K. Underwood
A Variable Long-precision Arithmetic Unit Design suitable for Reconfigurable Coprocessor Architectures
A. F. Tenca and M. D. Ercegovac
A Reconfigurable Multiplier Array for Video Image Processing Tasks, Suitable for Embedding in an FPGA Structure
S. D. Haynes and P. Y. K. Cheung
Poster Session 5
Paper Session 10 : Applications III
Accelerating Adobe Photo Using the XC6200 FPGA
S. Singh and R. Sloys
Analysis of the XC6000 Architecture for Embedded System Design
K. Weiss, R. Kistner, A. Kunzmann, W. Rosenstiel