FCCM 1997

The 5th IEEE International Symposium on
Field-Programmable Custom Computing Machines

April 16-18, 1997

Technical Programme : Papers

Wednesday, April 16, 1997
Paper Session 1 : Device Architecture
An FPGA Architecture for DRAM-based Systolic Computations
N. Margolus, Boston University and Massachusetts Institute of Technology
Garp: A MIPS Processor with a Reconfigurable Coprocessor
J. Hauser, J. Wawrzynek
A Time-Multiplexed FPGA
S. Trimberger, D. Carberry, A. Johnson, J. Wong
Poster Session 1
Paper Session 2: Communication Applications
An FPGA-Based Coprocessor for ATM Firewalls
J. McHenry, P. Dowd, T. Carrozzi, F. Pellegrino, W. Cocks
A Wireless LAN Demodulator in a Pamette: Design and Experience
T. McDermott, P. Ryan, M. Shand, D. Skellern, T. Percival, N. Weste
Paper Session 3: Run Time Reconfiguration
Incremental Reconfiguration for Pipelined Applications
H. Schmit
Compilation Tools for Run-Time Reconfigurable Designs
W. Luk, N. Shirazi, P. Cheung
A Dynamic Reconfiguration Run-Time System
J. Burns, A. Donlin, J. Hogg, S. Singh, M. de Wit
Poster Session 2
Paper Session 4: Architectures for Run Time Reconfiguration
The Swappable Logic Unit: A Paradigm for Virtual Hardware
G. Brebner
The Chimaera Reconfigurable Functional Unit
S. Hauck, T. Fry, M. Hosler, J. Kao
Thursday, April 17, 1997
Paper Session 5: Architecture
Computing Kernels Implemented with a Wormhole RTR CCM
R. Bittner and P. Athanas
Mapping Applications to the RaPiD Configurable Architecture
C. Ebeling, D. Cronquist, P. Franklin, J. Secosky, S. Berg
Defect Tolerance on the Teramac Custom Computer
B. Culbertson, R. Amerson, R. Carter, P. Kuekes, G. Snider
Poster Session 3
Paper Session 6: Performance
Systems Performance Measurement on PCI Pamette
L. Moll, M. Shand
The RAW Benchmark Suite: Computation Structures for General Purpose Computing
J. Babb, M. Frank, E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni, P. Finch, A. Agarwal
Paper Session 7: Software Tools
Automated Field-Programmable Compute Accelerator Design Using Partial Evaluation
Q. Wang, D. Lewis
FPGA Synthesis on the XC6200 using IRIS and Hades
R. Woods, S. Ludwig, J. Heron, D. Trainor, S. Gehring
High Level Compilation for Fine Grained FPGAs
M. Gokhale, E. Gomersall
Poster Session 4
Paper Session 8: CAD Applications
Acceleration of an FPGA Router
P. Chan, M. Schlag
Fault Simulation on Reconfigurable Hardware
M. Abramovici, P. Menon
Friday, April 18, 1997
Session 9: Image Processing Applications
Automated Target Recognition on Splash 2
M. Rencher, B. Hutchings
Real-Time Stereo Vision on the PARTS Reconfigurable Computer
J. Woodfill, B. Von Herzen
Increased FPGA Capacity Enables Scalable, Flexible CCMs: An Example from Image Processing
J. Greenbaum, M. Baxter
Poster Session 5
Session 10: Arithmetic Applications
Comparison of Arithmetic Architectures for Reed-Solomon Decoders in Reconfigurable Hardware
C. Paar, M. Rosner
Implementation of Single Precision Floating Point Square Root on FPGAs
Y. Li, W. Chu