Program

FCCM 2019 Preliminary Program

All times shown in PDT (UTC-7)

Sunday, April 28

RISC-V in Custom Computing Machines (3:30 – 5:30 PM PDT)

Dave Donofrio and Farzad Fatollahi-Fard (Lawrence Berkeley National Laboratory)

Dave and Farzed, leading researchers in RISC-V architecture, will present an overview of the processor from the FCCM perspective. Topics to be discussed include

  • Advantages/disadvantages compared to vendor provided soft processors
  • The various RISC-V flavors and configuration options
  • How a RISC-V core would get wrapped as IP and instantiated using vendor and/or open source tools
  • How to make the core connect to other soft or hard IP on the FPGA
  • How to extend the instruction set to create custom instructions in the FPGA fabric
  • Compiler tool chains and how to splice or download RISC-V programs onto the FPGA
  • How to run standalone programs
  • Examples or applications of RISC-V use in FPGA designs

Soft Processor Panel

The panel will offer their viewpoints on the roles and management of soft processor cores in custom computing machines.  Topics include core microarchitectures, configurability and options, cache and memory hierarchy, interaction of soft and hard processors, interfaces to hard and soft IP blocks, compiler and debug tools, software stack and run time.

Panelists:

  • Rob Aitken, ARM
  • Mike Butts, Compute Forest
  • Jan Gray, Gray Research
  • Guy Lemieux, University of British Columbia and Founder, CEO of VectorBlox
  • Ron Minnich, Google
  • Lesley Shannon, Simon Fraser University
  • Ted Speers, Microsemi

Monday, April 29

TimeSession TitlePresentation TitleAuthors
8:30OpeningOpening SessionRyan Kastner, André DeHon
8:45KeynoteHoF induction, KeynoteRahul Razdan
9:45Open Source ToolsYosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs (short)David Shah, Eddie Hung, Clifford Wolf, Miodrag Milanovic, Serge Bazanski and Dan Gisselquist
EFCAD – an Embedded FPGA CAD Tool Flow for Enabling On-Chip Self-Compilation (short)Khoa Pham, Malte Vesper, Dirk Koch and Eddie Hung
Maverick: A Stand-alone CAD Flow for Partially Reconfigurable FPGA ModulesDallon Glick, Jesse Grigg, Brent Nelson and Michael Wirthlin
10:15Poster Session 1Poster Session 1
11:00Machine Learning 1An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAsLiqiang Lu, Jiaming Xie, Ruirui Huang, Xiaoyuan Cui, Jiansong Zhang, Wei Lin and Yun Liang
LUTNet: Rethinking Inference in FPGA Soft LogicErwei Wang, James Davis, Peter Cheung and George Constantinides
PIR-DSP: An FPGA DSP-block Architecture for Multi-Precision Deep Neural NetworksSeyedramin Rasoulinezhad, Hao Zhou, Ling Li Wang and Philip H.W. Leong
Towards Efficient Deep Neural Network Training by FPGA-based Batch-level ParallelismCheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk and Ce Guo
12:20LunchLunch
1:35ToolsCRoute: A Fast High-Quality Timing-driven Connection-based FPGA RouterDries Vercruyce, Elias Vansteenkiste and Dirk Stroobandt
RapidRoute: Fast Assembly of Communication Structures on FPGAs (short)Leo Liu, Jay Weng and Nachiket Kapre
Generic Connectivity-Based CGRA Mapping via Integer Linear ProgrammingMatthew J. P. Walker and Jason H. Anderson
LAMDA: Learning-Assisted Multi-Stage Autotuning for FPGA Design Closure (short)Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu and Zhiru Zhang
Memory Mapping for Multi-Die FPGAsNils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk and Georgi Gaydadjiev
Impact of FPGA Architecture on Area and Performance of CGRA OverlaysIan Taras and Jason Anderson
3:05Poster Session 2Poster Session 2
3:50Applications 1π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation OptimizationShuzhen Qin, Qiang Liu, Bo Yu and Shaoshan Liu
Deep Packet Inspection in FPGAs via Approximate Nondeterministic AutomataMilan Ceska, Vojtěch Havlena, Lukas Holik, Jan Korenek, Ondrej Lengal, Denis Matousek, Jiří Matoušek, Jakub Semric and Tomas Vojnar
Active Stereo Vision with High Resolution on an FPGAMarc Pfeifer, Philipp Scholl, Rainer Voigt and Bernd Becker
Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPULicheng Guo, Ka Cheong Jason Lau, Zhenyuan Ruan, Peng Wei and Jason Cong
GhostSZ: A Transparent SZ Lossy Compression Framework with FPGAsQingqing Xiong, Chen Yang, Rushi Patel, Geng Tong, Anthony Skjellum and Martin Herbordt
An FPGA-based BWT Accelerator for Bzip2 Data Compression (short)Mau-Chung Frank Chang, Jason Cong, Zhenman Fang and Weikang Qiao
5:35Break
6:30Demo Night at Scripps ForumGrace Zgheib

Demo Night at the Beach

Demo Night is an opportunity for people to show off their latest and greatest systems, tools, and technologies in a relaxed atmosphere. See the latest technology from industry, meet with the leading FCCM researchers, demonstrate the latest and greatest research, and receive early feedback on work in progress.

Tuesday, April 30

TimeSession TitlePresentation TitleAuthors
8:30Simulation and InfrastructureMEG: A RISCV-based system simulation infrastructure for exploring memory optimization using FPGAs and Hybrid Memory CubeJialiang Zhang, Yang Liu, Gaurav Jain, Yue Zha, Jonathan Ta and Jing Li
Enhancing Butterfly Fat Tree NoCs for FPGAs with lightweight flow controlGurshaant Singh Malik and Nachiket Kapre
SimAcc: A Configurable Cycle-Accurate Simulator for customized accelerators on CPU-FPGAs SoCsKonstantinos Iordanou, Oscar Palomar, John Mawer, Cosmin Gorgovan, Andy Nisbet and Mikel Lujan
9:30Poster Session 3Poster Session 3
10:15Machine Learning 2Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGAZhe Lin, Sharad Sinha and Wei Zhang
Productively Generating High-Performance Spatial Hardware for Dense Tensor ComputationsNitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Christopher Hughes, Timothy Mattson and Pradeep Dubey
SparseHD: Algorithm-Hardware Co-Optimization for Efficient High-Dimensional ComputingMohsen Imani, Sahand Salamat, Behnam Khaleghi, Mohammad Samragh, Farinaz Koushanfar and Tajana Rosing
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNsEriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory Chen, Phil Knag, Raghavan Kumar, Ram Krishnamurthy and Debbie Marr
11:35Lunch
12:50ProgrammingDesign Patterns for Code Reuse in HLS Packet Processing PipelinesHaggai Eran, Lior Zeno, Zsolt István and Mark Silberstein
Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis DesignJeferson Santiago da Silva, François-Raymond Boyer and J.M. Pierre Langlois
Templatised soft floating-point for High-Level SynthesisDavid Thomas
Exploiting Irregular Memory Parallelism In Quasi-Stencils Through Nonlinear TransformationJuan Escobedo and Mingjie Lin
2:10Applications 2FP-AMR: A Reconfigurable Fabric Framework for Block-Structured Adaptive Mesh Refinement ApplicationsTianqi Wang, Tong Geng, Xi Jin and Martin Herbordt
Processor Assisted Scheduling for FPGA Accelerated Graph Processing on a Shared Memory PlatformYu Wang, James Hoe and Eriko Nurvitadhi
Compressed Sensing for MRI reconstruction on Intel HARPv2 (short)Yushan Su, Michael Anderson, Jonathan Tamir, Michael Lustig and Kai Li
2:55Poster Session 4Poster Session 4
3:40Security and ReliabilityFast Voltage Transients on FPGAs: Impact and Mitigation StrategiesLinda L. Shen, Ibrahim Ahmed and Vaughn Betz
FASE: FPGA Acceleration of Secure Function EvaluationSiam Umar Hussain and Farinaz Koushanfar
Efficient Hardware Acceleration for Design Diversity Calculation to mitigate Common Mode Failures (short)Maheshwaran Ramesh Babu, Farah Naz Taher, Anjana Balachandran and Benjamin Carrion Schafer
4:25ArithmeticRethinking Integer Divider Design for FPGA-based Soft ProcessorsEric Matthews, Alec Lu, Lesley Shannon and Zhenman Fang
High Precision, High Performance FPGA AddersMartin Langhammer, Bogdan Pasca and Gregg Baeckler
5:05CloseClosing SessionRyan Kastner, André DeHon
5:20End of Technical Program

Wednesday, May 1

TimeWorkshop Session 1Workshop Session 2  
8:00 Security for Custom Computing Machines
(Organizer: Dustin Richmond, University of Washington)
Xilinx ML Suite
(Organizer: Parimal Patel, Xilinx)
10:15Security for Custom Computing Machines
(Continued)
Xilinx RapidWright
(Chris Lavin, Xilinx)
12:15LunchLunch
1:15Edge Intelligence and FCCM: ML + IoT +FCCM
(Organizer: Marilyn Wolf, Georgia Tech)
Workshop by Intel FPGA group
(Organizers: David Kehlet, Oliver Tan, Larry Landis)
5:00Closing RemarksClosing Remarks