Title: Multi-tenant Cloud FPGAs: Commercial Need or Academic Pursuit?
Time: Sunday, May 9, 2021, 7:00 PM EDT
Cloud FPGAs have been the subject of intense academic and commercial
interest over the past five years. Although large state-of-the-art
FPGAs are typically used in these platforms, all commercial vendors
currently dedicate a cloud FPGA to a single user at a time. However, FPGA
multi-tenancy in which multiple independent users share a cloud FPGA at
the same time has obvious efficiencies and closely models cloud
virtual machine use. In this panel, we explore the commercial need for
cloud FPGA multi-tenancy and cloud FPGA programming models in general.
Does a cloud FPGA really need to be simultaneously shared? What
programming models for cloud FPGAs should be used to best access the
Russell Tessier, University of Massachusetts Amherst
Russell Tessier is a professor of electrical and computer engineering at the University of Massachusetts Amherst. He has performed research in FPGAs and reconfigurable computing for 30 years. He was a founder of Virtual Machine Works, a logic emulation company which is now owned by Seimens. Prof. Tessier’s recent research interests include FPGA security and embedded system design.
Paul Chow is a professor in the faculty of The Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. He is a Fellow of the IEEE and Fellow of the Engineering Institute of Canada. His main research is about making FPGAs into computing devices so that applications can be easily deployed. In particular, he wants to do this at scale in a heterogeneous environment where FPGAs seamlessly interact with CPUs and other devices, all as peers, and transparently to the application.
Nachiket Kapre is an Associate Professor in the Department of Electrical and Computer Engineering at University of Waterloo, Canada. He was previously an Assistant Professor at Nanyang Technological University, Singapore in the School of Computer Engineering. He has received his M.S in Electrical Engineering (2005) and Computer Science (2006) and a PhD in Computer Science (2010) from California Institute of Technology, Pasadena. He is primarily interested in understanding and exploiting the potential of parallel, spatial architectures such as FPGAs for energy-efficient computing. His research has won best paper awards at FPT 2011, FPL 2015, CASES 2016, TRETS 2017, and FPT 2019.
Jakub Szefer’s research focuses on computer architecture and hardware security. His research encompasses secure processor architectures, cloud security, FPGA attacks and defenses, and hardware FPGA implementation of cryptographic algorithms.