The 12th Annual IEEE Symposium on 
Field-Programmable Custom Computing Machines 
FCCM '04 
Napa, California 
20 - 23 April, 2004

Final Program

Tuesday 20 April 2004

7:00pm - 9:00pm
Registration and Reception

Wednesday 21 April 2004

8:30am - 10:00am
Session 1: Architecture
Chair: Scott Hauck, University of Washington

 
Authors: P. James-Roxby, G. Brebner, D. Bemmann
Organization: Xilinx and Humboldt University
Title:  Time-Critical Software Deceleration in an FCCM
 
Authors: A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi, M. Vanier, M. Wrighton
Organization: Caltech
Title: Design Patterns for Reconfigurable Computing
 
Authors: M. Vuletic, L. Pozzi and P. Ienne
Organization: Swiss Federal Institute of Technology Lausanne,
Title: Virtual Memory Window for Portable Reconfigurable Cryptography Coprocessor

10:00am - 11:00am
Poster Session 1 (see below)

11:00am - 12:00pm
Session 2: Tools I
Chair: Katherine Compton, University of Wisconsin

 
Authors: G. Mittal, D. Zaretsky, X. Tang, P. Banerjee
Organization: Northwestern University
Title: Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs
 
Authors: J. Ou and V. Prasanna
Organization: University of Southern California
Title: PyGen: A MATLAB/Simulink based Tool for Parameterized and Energy

1:30pm - 3:00pm
Session 3: Arithmetic I
Chair: Tom Kean, Algotronix

 
Authors: M.L. Chang and S. Hauck
Organization: University of Washington
Title: Automated Least-Significant Bit Datapath Optimization for FPGAs
 
Authors: K.H. Tsoi, C.H. Ho, H.C. Yeung and P.H.W. Leong
Organization: Chinese University of Hong Kong
Title:  An Arithmetic Library and its Application to the N-body Problem
 
Authors: A. Gaffar, O. Mencer, W. Luk and P.Y.K. Cheung
Organization: Imperial College London
Title: Unifying Bit-width Optimisation for Fixed-point and Floating-point Designs

3:00pm - 4:00pm
Poster Session 2 (see below)

4:00pm - 5:00pm
Session 4: Communications Applications
Chair: Wayne Luk, Imperial College

 
Authors: J. Liang, R. Tessier and D. Goeckel
Organization: University of Massachusetts
Title:  A Dynamically Reconfigurable, Power-Efficient Turbo Decoder
 
Authors: D-U Lee, W Luk, C Wang, C Jones, M Smith, J Villasenor
Organization: Imperial College of Science Technology and Medicine
Title: A Flexible Hardware Encoder for Low-Density Parity-Check Codes

Thursday 22 April 2004

8:30am - 10:00am
Session 5: Networking I
Chair: Brad Hutchings, Tabula

 
Authors: R. Krishnamurthy, S. Yalamanchili, K. Schwan, R. West
Organization: Georgia Tech
Title: ShareStreams: A Scalable Architecture and Hardware Support for High-Speed
 QoS Packet Schedulers
 
Authors: Y. Cho and W. Mangione-Smith
Organization: UCLA
Title: Deep Packet Filter with Dedicated Logic and Read Only Memories
 
Authors: Z. Baker and V. Prasanna
Organization: University of Southern California
Title: A Methodology for Synthesis of Efficient Intrusion Detection
 Systems on FPGAs

10:00am - 11:00am
Poster Session 3 (see below)

11:00am - 12:00pm
Session 6: Applications I
Chair: Satnam Singh, Microsoft

 
Authors: M. Leeser, S. Miller and H. Yu
Organization: Northeastern University
Title: Smart Camera Based on Reconfigurable Hardware Enables
 Diverse Real-time Applications
 
Authors: J. Durbano, F. Ortiz, J. Humphrey, P. Curt, D. Prather
Organization: EM Photonics and University of Delaware
Title: FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method

1:30pm - 3:00pm
Session 7: Tools II
Chair: Mike Butts, Tabula

 
Authors: H. Al Atat and I. Ouaiss
Organization: Lebanese American University
Title: Register Binding for FPGAs with Embedded Memory
 
Authors: M. Tahoori and S. Mitra
Organization: Northeastern Univ. and Intel
Title: Defect and Fault Tolerance for Reconfigurable Molecular Computing
 
Authors: M. Gokhale, C. Ahrens, J. Frigo, C. Wolinski
Organization: Los Alamos National Lab
Title: Communications Scheduling for Concurrent Processes on Reconfigurable Computers

3:00pm - 4:00pm
Poster Session 4 (see below)

4:00pm - 5:00pm
Session 8: Applications II
Chair: Maya Gokhale, Los Alamos National Lab

 
Authors: N. Azizi, I. Kuon, A. Egier, A. Darabiha and P. Chow
Organization: University of Toronto
Title: Reconfigurable Molecular Dynamics Simulator
 
Authors: C. He, M. Lu, C. Sun
Organization: Texas A&M University
Title: Accelerating Seismic Migration Using FPGA-based Coprocessor Platform

Friday 23 April 2004

8:30am - 10:00am
Session 9: Arithmetic II
Chair: Andre' DeHon, Caltech

 
Authors: Keith D. Underwood and K. Scott Hemmert
Organization: Sandia National Labs
Title: Closing the gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS
  Performance
 
Authors: C. Doss and R. Riley
Organization: North Carolina A & T and AFRL
Title: FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit
 
Authors: S. Krueger, P-M. Seidel
Organization: Texas Instruments and Southern Methodist University
Title: On-Line IEEE Floating-Point Arithmetic for FPGAs

11:00am - 12:00pm
Session 10: Networking II
Chair: Jeffrey Arnold, Stretch

 
Authors: C. Clark and D. Schimmel
Organization: Georgia Institute of Technology, Atlanta, GA
Title: Scalable Multi-Pattern Matching on High-Speed Networks
 
Authors: Ioannis Sourdis and Dionisios Pnevmatikatos
Organization: Technical University of Crete
Title: Pre-decoded CAMs for Efficient and High-Speed NIDS Pattern Matching

Wednesday 21 April 2004
10:00am - 11:00am
Poster Session 1

 
Authors: G. Kuzmanov, G. Gaydadjiev, S. Vassiliadis
Organization: Delft University of Technology, The Netherlands
Title: The MOLEN Processor Prototype
 
Authors: S. Khawam, T. Arslan and F. Westall
Organization: University of Edinburgh
Title: Switch-Box Design for Synthesizable Coarse-Grain Reconfigurable
 Arrays for System-on-Chip Applications
 
Authors: D. Wentzlaff and A. Agarwal
Organization: MIT
Title: A Quantitative Comparison of Reconfigurable, Tiled, and
 Conventional Architectures on Bit-level Computation
 
Authors: S. Wallner
Organization: Technical University Hamburg-Harburg
Title: Design Methodology of a Configurable System-on-Chip Architecture
 
Authors: D. Hanna, R. Haskell
Organization: Oakland University
Title: Flowpaths: A New Approach to the Algorithmic Design of Microsystems
 
Authors: N. Suzuki, H. Amano et. al.
Organization: Keio University and NEC
Title: Implementing and Evaluating Stream Applications
 on the Dynamically Reconfigurable Processor
 
Authors: P. James-Roxby, P. Schumacher and Charlie Ross
Organization: Xilinx and Colorado State University
Title: A Single Program Multiple Data Parallel Processing Platform for FPGAs
 
Authors: S. Lange and M. Middendorf
Organization: University of Leipzig
Title: Hyperreconfigurable Architectures for Fast Runtime Reconfiguration
 
Authors: Michail D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, C. Goutis
Organization: University of Patras
Title: Accelerating DSP Applications on a Mixed Granularity Platform with a new
 Reconfigurable Coarse-Grain Data-Path
 
Authors: A. Lodi, R. Giansante, C. Ciesa, L. Ciccarelli, M. Toma and F. Campi
Organization: University of Bologna
Title: Design of Routing Switches for Multi-Context FPGAs
 
Authors: Peter Sedcole, Peter Y.K. Cheung and George Constantinides
Organization: Imperial College of Science Technology and Medicine
Title: A structured system methodology for FPGA based System-on-a-Chip design

Wednesday 21 April 2004
3:00pm - 4:00pm
Poster Session 2

 
Authors: D. Eilers, H. Steckenbiller, A. Herkersdorf
Organization: Fraunhofer Institute for Communication Systems
Title: Buffer Schemes for Runtime Reconfiguration of Function Variants
 in Communication Systems
 
Authors: G. Leyva, G. Caffarena, C. Carreras, O. Nieto-Taladriz
Organization: Universidad Politecnica de Madrid
Title: A generator of high-speed floating-point modules
 
Authors: A. Tenca, A. Chaitheerayanon, E. Khair
Organization: Oregon State University
Title: Flexible Modular Multiplier Design for FPGAs
 
Authors: J. Schier, A. Hermanek
Organization: Academy of Sciences of the Czech Republic
Title: FPGA implementation of recursive QR update using logarithmic arithmetic
 
Authors: D. Boppana, K. Dhanoa, J. Kempa
Organization: Altera
Title: FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm
 
Authors: W. Gross, F. Kschischang, P.G. Gulak
Organization: McGill University and University of Toronto
Title: An FPGA Interpolation Processor for Soft-Decision Reed-Solomon
 Decoding
 
Authors: V. Tomashau, T. Kean
Organization: Algotronix
Title: Implementation and Validation of an Advanced Encryption Standard
 (AES) IP Core
 
Authors: J. Kwok-San Lee, B. Lee, J. Thorpe, K. Andrews, S. Dolinar, J. Hamkins
Organization: Caltech and JPL
Title: Design and Implementation of a Structured LDPC Decoder on FPGA
 
Authors: C. McIvor, M. McLoone, J. McCanny
Organization: Queen's University Belfast,
Title: FPGA Montgomery Multiplier Architectures - a Comparison
 
Authors: A. Hodjat and I. Verbauwhede
Organization: UCLA
Title: A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
 
Authors: G. Sutter, G. Bioul, and J-P. Deschamps
Organization: U. Autonoma de Madrid, U. Nacional del Centro, Tandil Argentina, U. Rovira i Virgili
Title: Improved FPGA Dividers for Floating Point Operations

Thursday 22 April 2004
10:00am - 11:00am
Poster Session 3

 
Authors: Tom Van Court and Martin Herbordt
Organization: Boston University
Title: FPGA Acceleration of Rigid Molecule Interactions
 
Authors: J. Pimentel, H. Le-Huy, G. Sybille
Organization: Cisco Systems
Title: A Scalable Custom Real Time Simulator for Power Systems
 
Authors: S. Yusuf, W. Luk, G. Brown
Organization: Imperial College of Science Technology and Medicine, Indiana University
Title: Hardware Monitoring of Network Traffic
 
Authors: S. Dharmapurikar, M. Attig, J. Lockwood
Organization: Washington University in St. Louis,
Title: Design and Implementation of a String Matching System
 for Network Intrusion Detection using FPGA-based Bloom Filters
 
Authors: Sreesa Akella and James P. Davis
Organization: University of South Carolina
Title: Custom Computing for Phylogenetics: Exploring the Solution Space
 for UPGMA
 
Authors: J. Li, C. Papachristou and R. Shekhar
Organization: Case Western Reserve University and Cleveland Clinic Foundation
Title: A Reconfigurable SoC Architecture and Caching Scheme
 for 3D Medical Image Processing
 
Authors:  D. Allred, W. Huang, V. Krishnan, H. Yoo, D. Anderson
Organization: Georgia Institute of Technology
Title: An FPGA Implementation for a High Throughput Adaptive
 Filter Using Distributed Arithmetic
 
Authors: S. Phillips, A. Sharma and S. Hauck
Organization: University of Washington
Title: Automating the Layout of Reconfigurable Subsystems Via Template
 Reduction
 
Authors: N. Steiner and P. Athanas
Organization: Virginia Tech
Title: An Alternate Wire Database for Xilinx FPGAs
 
Authors: H. Song, J. Lu, J. Lockwood, J. Moscola
Organization: Washington University in St. Louis
Title: Secure Remote Configuration of Field-programmable Network Devices
 
Authors: L. Bu and J. Chandy
Organization: University of Connecticut
Title: Hardware Based Intrustion Detection using Reconfigurable Hardware

Thursday 22 April 2004
3:00pm - 4:00pm
Poster Session 4

 
Authors: Matthias Dyer
Organization: Swiss Federal Institute of Technology (ETH) Zuerich
Title: Efficient Execution of Process Networks on a Dynamic
 Reconfigurable Hardware Virtual Machine
 
Authors: A. Cappelli, A. Lodi, C. Mucci, M. Toma, F. Campi
Organization: University of Bologna
Title: A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow
 
Authors: S. Mohanty and V. Prasanna
Organization: University of Southern California
Title: Duty Cycle Aware Application Design using FPGAs
 
Authors: R. Mukherjee and S. Memik
Organization: Northwestern University
Title: Power Management for High-Performance FPGAs: Power-Driven Design
 Partitioning
 
Authors: Gareth W. Morris, George A. Constantinides, and Peter Y.K. Cheung
Organization: Imperial College of Science Technology and Medicine
Title: Migrating Functionality from ROMs to Embedded Multipliers
 
Authors: G. Constantinides, A. Miah, N. Sidahao
Organization: Imperial College of Science Technology and Medicine
Title: Word-Length Optimization of Folded Polynomial Evaluation
 
Authors: Gregory V. Larchev
Organization: NASA Ames Research Center
Title: Novel use of reconfigurability, evolvable hardware.
 Hardware-in-the-Loop Evolution of a 3-bit Multiplier
 
Authors: João M. P. Cardoso
Organization: University of Algarve
Title: Self Pipelining of Loops in Acknowledge-Token Data-Driven
 Reconfigurable Architectures
 
Authors: C. Ross and W. Bohm
Organization: Colorado State University
Title: Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems
 
Authors: Emre Ozer
Organization: Trinity College, Dublin, Ireland
Title: Fine-tuning Instruction-level Parallelism for Increasing
 Performance of DSP Applications on FPGAs
 
Authors: W. Bohm, J. Hammes
Organization: Colorado State and SRC Computers
Title: Implementing a Honeywell Wavelet Benchmark on the SRC-6E

FCCM / 15 April 2004 / fccm@fccm.org