The 7th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines
FCCM '99
Marriott at Napa Valley, Napa, California
20-23 April 1999

Program

7:00pm - 9:00pm
Registration and Reception

8:30am - 10:00am
Session 1: Tools

Authors:      Joao M. P. Cardoso and Horacio C. Neto

Organization: INESC, Portugal

Title:        Macro-Based Hardware Compilation of Java(tm) Bytecodes into a

              Dynamic Reconfigurable Computing System

Authors:      Brad Hutchings, et. al.

Organization: Brigham Young University

Title:        A CAD Suite for High-Performance FPGA Design

Authors:      Satnam Singh and Carl Johan Block

Organization: Xilinx Inc., Prover Technology and Chalmers University of Technology

Title:        Formal Verification of Reconfigurable Cores

10:00am - 11:00am
Coffee break and Poster Session

11:00am - 12:00pm
Session 2: Network Applications

Authors:      T. Miyazaki, T. Murooka, M. Katayama, A. Takahara

Organization: NTT Optical Network Systems Labs

Title:        Transmutable Telecom System and Its Application

Authors:      Jason Hess, David Lee, Scott Harper, Mark Jones and Peter Athanas

Organization: Virginia Polytechnic Institute and State University

Title:        Implementation and Evaluation of a Prototype Reconfigurable Router

12:00pm - 1:30pm
Lunch break

1:30pm - 3:00pm
Session 3: Compilation

Authors:      Markus Weinhardt and Wayne Luk

Organization: Imperial College

Title:        Pipeline Vectorization for Reconfigurable Systems

Authors:      Maya Gokhale and Jan Stone

Organization: Sarnoff Corp.

Title:        Automatic Allocation of Arrays to Memories in FPGA Processors

              With Multiple Memory Banks

Authors:      Jonathan Babb et. al.

Organization: Massachusetts Institute of Technology

Title:        Parallelizing Applications into Silicon

3:00pm - 4:00pm
Coffee break and Poster Session

4:00pm - 5:00pm
Session 4: Architectures

Authors:      Michael Piacentino, Gooitzen van der Wal and Michael Hansen

Organization: Sarnoff Corp.

Title:        Reconfigurable Elements for a Video Pipeline Processor

Authors:      Bernardo Kastrup, Arjan Bink and Jan Hoogerbrugge

Organization: Philips Research Laboratories

Title:        ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator

7:00pm - 10:00pm
Buffet and Demo Night

8:30am - 10:00am
Session 5: Tools

Authors:      Srihari Cadambi and Seth Copen Goldstein

Organization: Carnegie Mellon University

Title:        CPR: A Configuration Profiling Tool

Authors:      Nicholas McKay and Satnam Singh.

Organization: University of Glasgow and Xilinx Inc.

Title:        Debugging Techniques for Dynamically Reconfigurable Hardware

Authors:      Milan Vasilko and David Cabanis

Organization: Bournemouth University and Esperan Ltd.

Title:        Improving Simulation Accuracy in Design Methodologies

              for Dynamically Reconfigurable Logic Systems

10:00am - 11:00am
Coffee break and Poster Session

11:00am - 12:00pm
Session 6: Graphics Applications

Authors:      W. Luk, T.K. Lee,

J.R. Rice, N. Shirazi and P.Y.K. Cheung

Organization: Imperial College

Title:        Reconfigurable Computing for Augmented Reality

Authors:      Laurent Moll, Alan Heirich and Mark Shand

Organization: Compaq Computer Corp.

Title:        Sepia: scalable 3D compositing using PCI Pamette

12:00pm - 1:30pm
Lunch break

1:30pm - 2:00pm
Invited Talk

Speaker:      Philip Kuekes

Organization: HP Laboratories

Title:        Molecular Manufacturing: Beyond Moore's Law

2:00pm - 3:00pm
Session 7: Applications

Authors:      Zhen Luo, Margaret Martonosi, Pranav Ashar

Organization: Princeton University

Title:        An Edge-Endpoint-Based Configurable Hardware Architecture for

              VLSI CAD Layout Design Rule Checking

Authors:      J. Carlos Alves et. al.

Organization: INESC, Portugal

Title:        Fafner--Accelerating Nesting Problems with FPGAs

3:00pm - 4:00pm
Coffee break and Poster Session

4:00pm - 5:00pm
Session 8: DSP Applications

Authors:      Tyler Moeller and David R. Martinez

Organization: MIT Lincoln Lab

Title:        Field Programmable Gate Array Based Radar Front-End

              Digital Signal Processing

Authors:      Daniel Benyamin, Wayne Luk and John Villasenor

Organization: UCLA and Imperial College

Title:        Optimizing FPGA-based vector product designs

8:30am - 10:00am
Session 9: Run Time Systems

Authors:      Ronald Laufer, R. Reed Taylor and Herman Schmit

Organization: Carnegie Mellon University

Title:        PCI-PipeRench and the SwordAPI: A System for Stream-based

              Reconfigurable Computing

Authors:      Andrew A. Chien and Jay H. Byun

Organization: University of California, San Diego and University of Illinois

Title:        Safe and Protected Execution for the Morph/AMRM

              Reconfigurable Processor

Authors:      Mark Jones et. al.

Organization: Virginia Tech and USC/ISI-East

Title:        Implementing an API for Distributed Adaptive Computing Systems

10:00am - 10:30am
Coffee break

10:30am - 12:00pm
Session 10: Arithmetic

Authors:      Gerardo Orlando and Christof Paar

Organization: GTE Government Systems and Worcester Polytechnic Institute

Title:        A Super-Serial Galois Fields Multiplier for FPGAs and

              its Application to Public-Key Algorithms

Authors:      M. P. Leong et. al.

Organization: Chinese University of Hong Kong

Title:        Automatic Floating to Fixed Point Translation

              and its Application to Post--Rendering 3D Warping

Authors:      Kiran Bondalapati and Viktor K. Prasanna

Organization: University of Southern California

Title:        Dynamic Precision Management for Loop Computations on

              Reconfigurable Architectures

FCCM / 31 Mar 1999 / fccm@fccm.org