The 6th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines
FCCM '98
Marriott at Napa Valley, Napa, California
14-17 April 1998

Preliminary Program

7:00pm - 9:00pm
Registration and Reception

8:30am - 10:00am
Session 1: Architectures I

Authors:      T. Miyamori and K. Olukotun

Organization: Stanford University

Title:        A Quantitative Analysis of Reconfigurable Coprocessors

              for Multimedia Applications

Authors:      C.A. Moritz, D. Yeung and A. Agarwal

Organization: MIT LCS

Title:        Exploring Optimal Cost-Performance Designs for

              Raw Microprocessors

Authors:      C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt,

              J. Arnold and M. Gokhale

Organization: National Semiconductor and Sarnoff Corp.

Title:        The NAPA Adaptive Processing Architecture

10:00am - 11:00am
Coffee break and Poster Session

11:00am - 12:00pm
Session 2: Special Purpose Systems

Authors:      S. Swanchara, S. Harper and P. Athanas

Organization: Virginia Tech

Title:        A Stream-Based Configurable Computing Radio Testbed

Authors:      A. Dollas, E. Sotiriades and A. Emmanonelides

Organization: Technical University of Crete

Title:        Architecture and Design of GE1, a FCCM for

              Golomb Ruler Derivation

12:00pm - 1:30pm
Lunch break

1:30pm - 3:00pm
Session 3: Architectures II

Authors:      A. Ohta, T. Isshiki and H. Kunieda

Organization: Tokyo Institute of Technology

Title:        New FPGA Architecture for Bit-Serial Pipeline Datapath

Authors:      K. Nagami, K. Oguri, T. Shiozawa, H. Ito and R. Konishi

Organization: NTT Optical Network Systems Laboratories

Title:        Plastic Cell Architecture: Towards Reconfigurable Computing

              for General Purpose

Authors:      S. M. Scalera and J. R. Vazquez

Organization: Lockheed Sanders

Title:        The Design and Implementation of a Context Switching FPGA

3:00pm - 4:00pm
Coffee break and Poster Session

4:00pm - 5:00pm
Session 4: Applications I

Authors:      R. Hudson, D. Lehn and P. Athanas

Organization: Virginia Tech

Title:        A Run-Time Reconfigurable Engine for Image Interpolation

Authors:      M. Shand and L. Moll

Organization: DEC

Title:        Hardware/Software Integration in Solar Polarimetry

7:00pm - 10:00pm
Buffet and Demo Night

8:30am - 10:00am
Session 5: Compilers

Authors:      A.A. Duncan, D.C. Hendry, P. Cray

Organization: University of Aberdeen

Title:        An Overview of the COBRA-ABS High Level Synthesis System for

              Multi-FPGA Systems

Authors:      D. Cronquist, P. Franklin, S. Berg and C. Ebeling

Organization: University of Washington

Title:        Specifying and Compiling Applications for RaPiD

Authors:      M.B. Gokhale and J.M. Stone

Organization: Sarnoff Corp.

Title:        NAPA C: Compiling for a Hybrid RISC/FPGA Architecture

10:00am - 11:00am
Coffee break and Poster Session

11:00am - 12:00pm
Session 6: Tools for Run Time Reconfiguration

Authors:      S. Hauck, Z. Li and E. Schwabe

Organization: Northwestern University

Title:        Configuration Compression for the Xilinx XC6200 FPGA

Authors:      N. Shirazi, W. Luk and P.Y.K. Cheung

Organization: Imperial College

Title:        Automating Production of Run-Time Reconfigurable Designs

12:00pm - 1:30pm
Lunch break

1:30pm - 3:00pm
Session 7: Module Generation

Authors:      M. Chu, K. Sulimma, N. Weaver, A. DeHon, J. Wawrzynek

Organization: UCBerkeley

Title:        Object Oriented Circuit-Generators in Java

Authors:      O. Mencer, M. Morf and M. J. Flynn

Organization: Stanford University

Title:        PAM-Blox: High Performance FPGA Design for Adaptive Computing

Authors:      P. Bellows and B. Hutchings

Organization: Brigham Young University

Title:        JHDL - An HDL for Reconfigurable Systems

3:00pm - 4:00pm
Coffee break and Poster Session

4:00pm - 5:00pm
Session 8: Applications II

Authors:      P. Zhong, M. Martonosi, P. Ashar and S. Malik

Organization: Princeon University and NEC CCRL

Title:        Accelerating Boolean Satisfiability with Configurable Hardware

Authors:      A. Rashid, J. Leonard and W.H. Mangione-Smith

Organization: UCLA

Title:        Dynamic Circuit Generation for Solving Specific Problem

              Instances of Boolean Satisfiability

8:30am - 10:00am
Session 9: Arithmetic

Authors:      W. Ligon, S. McMillan, G. Monn, F. Stivers and K. Underwood

Organization: Clemson University

Title:        A Re-evaluation of the Practicality of Floating Point

              Operations on FPGAs

Authors:      A. F. Tenca and M. D. Ercegovac

Organization: UCLA

Title:        A Variable Long-precision Arithmetic Unit Design suitable for

              Reconfigurable Coprocessor Architectures

Authors:      S. D. Haynes and P. Y. K. Cheung

Organization: Imperial College

Title:        A Reconfigurable Multiplier Array for Video Image Processing

              Tasks, Suitable for Embedding in an FPGA Structure

10:00am - 11:00am
Coffee break and Poster Session

11:00am - 12:00pm
Session 10: Applications III

Authors:      S. Singh and R. Sloys

Organization: Xilinx

Title:        Accelerating Adobe Photo Using the XC6200 FPGA

Authors:      K. Weiss, R. Kistner, A. Kunzmann, W. Rosenstiel

Organization: University of Karlsruhe and University of Tubingen

Title:        Analysis of the XC6000 Architecture for Embedded System Design

FCCM / 12 Mar 1998 / fccm@fccm.org