The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Marriott at Napa Valley, Napa, California April 16 - April 18, 1997 Preliminary Program http://www.fccm.org Tuesday, April 15, 1997 7:00 - 9:00 PM Registration and Reception Wednesday, April 16, 1997 7:30 AM Registration Opens 8:30 - 10:00 AM Session 1 10:00 - 11:00 AM Break and Poster Session 1 11:00 - 12:00 PM Session 2 12:00 - 1:30 PM Lunch 1:30 - 3:00 PM Session 3 3:00 - 4:00 PM Break and Poster Session 2 4:00 - 5:00 PM Session 4 5:00 - 6:00 PM Open 6:00 - 9:00 PM Demonstrations and Reception Thursday, April 17, 1997 8:00 AM Registration opens 8:15 - 8:30 AM Administrative updates 8:30 - 10:00 AM Session 5 10:00 - 11:00 AM Break and Poster Session 3 11:00 - 12:00 PM Session 6 12:00 - 1:30 PM Lunch 1:30 - 3:00 PM Session 7 3:00 - 4:00 PM Break and Poster Session 4 4:00 - 5:00 PM Session 8 5:00 - 7:00 PM Open 7:00 - 10:00 PM Banquet Friday, April 18, 1997 8:00 AM Registration opens 8:15 - 8:30 AM Administrative updates 8:30 - 10:00 AM Session 9 10:00 - 11:00 AM Break and Poster Session 5 11:00 - 12:00 PM Session 10 12:00 - 12:30 PM Closing Remarks & Feedback for next year Wednesday, April 18, 1997 (Day 1) Session 1: Device Architecture Title: An FPGA Architecture for DRAM-based Systolic Computations Authors: N. Margolus Organizations: Boston University and Massachusetts Institute of Technology Title: Garp: A MIPS Processor with a Reconfigurable Coprocessor Authors: J. Hauser, J. Wawrzynek Organization: University of California, Berkeley Title: A Time-Multiplexed FPGA Authors: S. Trimberger, D. Carberry, A. Johnson, J. Wong Organizations: Xilinx, Inc. Poster Session 1 Session 2: Communication Applications Title: An FPGA-Based Coprocessor for ATM Firewalls Authors: J. McHenry, P. Dowd, T. Carrozzi, F. Pellegrino, W. Cocks Organization: National Security Agency and University of Maryland Title: A Wireless LAN Demodulator in a Pamette: Design and Experience Authors: T. McDermott, P. Ryan, M. Shand, D. Skellern, T. Percival, N. Weste Organization: Macquarie University, CSIRO, and Digital Equipment Corp. LUNCH Session 3: Run Time Reconfiguration Title: Incremental Reconfiguration for Pipelined Applications Authors: H. Schmit Organization: Carnegie Mellon University Title: Compilation Tools for Run-Time Reconfigurable Designs Authors: W. Luk, N. Shirazi, P. Cheung Organization: Imperial College Title: A Dynamic Reconfiguration Run-Time System Authors: J. Burns, A. Donlin, J. Hogg, S. Singh, M. de Wit Organization: University of Glasgow Poster Session 2 Session 4: Architectures for Run Time Reconfiguration Title: The Swappable Logic Unit: A Paradigm for Virtual Hardware Authors: G. Brebner Organization: University of Edinburgh Title: The Chimaera Reconfigurable Functional Unit Authors: S. Hauck, T. Fry, M. Hosler, J. Kao Organization: Northwestern University Thursday, April 17, 1997 (Day 2) Session 5: Architecture Title: Computing Kernels Implemented with a Wormhole RTR CCM Authors: R. Bittner and P. Athanas Organization: Virginia Polytechnic Institute Title: Mapping Applications to the RaPiD Configurable Architecture Authors: C. Ebeling, D. Cronquist, P. Franklin, J. Secosky, S. Berg Organization: University of Washington Title: Defect Tolerance on the Teramac Custom Computer Authors: B. Culbertson, R. Amerson, R. Carter, P. Kuekes, G. Snider Organizations: Hewlett-Packard Laboratories Poster Session 3 Session 6: Performance Title: Systems Performance Measurement on PCI Pamette Authors: L. Moll, M. Shand Organizations: Pole Universitaire Leonard de Vinci and Digital Equipment Corp. Title: The RAW Benchmark Suite: Computation Structures for General Purpose Computing Authors: J. Babb, M. Frank, E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni, P. Finch, A. Agarwal Organization: Massachusetts Institute of Technology LUNCH Session 7: Software Tools Title: Automated Field-Programmable Compute Accelerator Design Using Partial Evaluation Authors: Q. Wang, D. Lewis Organization: University of Toronto Title: FPGA Synthesis on the XC6200 using IRIS and Hades Authors: R. Woods, S. Ludwig, J. Heron, D. Trainor, S. Gehring Organization: The Queen's University of Belfast and ETH Zurich Title: High Level Compilation for Fine Grained FPGAs Authors: M. Gokhale, E. Gomersall Organization: David Sarnoff Research Center and National Semiconductor Poster Session 4 Session 8: CAD Applications Title: Acceleration of an FPGA Router Authors: P. Chan, M. Schlag Organization: University of California, Santa Cruz Title: Fault Simulation on Reconfigurable Hardware Authors: M. Abramovici, P. Menon Organization: Lucent Technologies and University of Massachusetts Friday, April 18, 1997 (Day 3) Session 9: Image Processing Applications Title: Automated Target Recognition on Splash 2 Authors: M. Rencher, B. Hutchings Organization: Brigham Young University Title: Real-Time Stereo Vision on the PARTS Reconfigurable Computer Authors: J. Woodfill, B. Von Herzen Organization: Interval Research Corp. and Rapid Prototypes, Inc. Title: Increased FPGA Capacity Enables Scalable, Flexible CCMs: An Example from Image Processing Authors: J. Greenbaum, M. Baxter Organization: Ricoh California Research Center Poster Session 5 Session 10: Arithmetic Applications Title: Comparison of Arithmetic Architectures for Reed-Solomon Decoders in Reconfigurable Hardware Authors: C. Paar, M. Rosner Organization: Worcester Polytechnic Institute Title: Implementation of Single Precision Floating Point Square Root on FPGAs Authors: Y. Li, W. Chu Organization: University of Aizu