FCCM '05 

Preliminary Program

Sunday 17 April 2005

Registration and reception, 7:00pm – 9:00pm

Monday 18 April 2005

Session 1:  Applications I

8:30 – 10:00

Title:  Efficient Hardware Data Mining with the Apriori
 Algorithm on FPGAs
Authors:  Zachary K. Baker, Viktor K. Prasanna
Organization:  University of Southern California
 
Title:  A Novel 2D Filter Design Methodology for Heterogeneous Devices 
Authors:  Christos-Savvas Bouganis, George A. Constantinides, Peter Y.K. Cheung
Organization:  Imperial College
 
Title:  Prototyping Architectural Support for Program Rollback Using FPGAs 
Authors:  Radu Teodorescu, Josep Torrellas
Organization:  UIUC

Poster Session 1

10:00 – 11:00

Session 2: Architecture

11:00 – 12:00

 
Title:  Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
Authors:  Zion Kwok, Steven J.E. Wilton
Organization:  University of British Columbia
 
Title:  Handling Different Computational Granularity by a Reconfigurable IC featuring Embedded FPGAa and a Network-on-Chip
Authors:  Francesco Lertora, Michele Borgatti
Organization:  ST Microelectronics

Session 3: Tools I

1:30 – 3:00

 
Title:  A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Authors:  Roman Lysecky, Frank Vahid, Sheldon X.-D. Tan
Organization:  University of California, Riverside
 
Title:  Simplifying the Integration of Processing Elements in Computing Systems using a Programmable Controller
Authors:  Lesley Shannon, Paul Chow
Organization:  University of Toronto
 
Title:  Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures
Authors:  Pedro C. Diniz
Organization:  University of Southern California/ISI

Poster Session 2

3:00 – 4:00

Session 4: Graphics

4:00 – 5:00

 
Title:  FPGA Particle Graphics Hardware
Authors:  John S. Beeckler, Warren J. Gross
Organization:  McGill University
 
Title:  Reconfigurable Designs for Radiosity
Authors:  Paul Baker, Tim Todman, Henry Styles, Wayne Luk
Organization:  Imperial College

Demo Night

7:00 – 9:00

Tuesday 19 April 2005

Session 5:  Applications II

8:30 – 10:00

 
Title:  Hardware Factorization Based on Elliptic Curve Method
Authors:  Martin Simka, **Jan Pelzl, ***Thorsten Kleinjung, Milos Drutarovsky, ****Viktor Fischer, **Christof Paar
Organization:  Technical University of Kosice, Ruhr University**, University of Bonn***, Universite Jean Monnet****
 
Title:  Metropolitan Road Traffic Simulation on FPGAs
Authors:  Justin L. Tripp, Henning S. Mortveit, Anders A. Hansson, Maya Gokhale
Organization:  Los Alamos National Laboratories
 
Title:  Time Domain Numerical Simulation for Transient Wave Equations on Reconfigurable Coprocessor Platform
Authors:  Chuan He, Wei Zhao, Mi Lu
Organization:  Texas A&M University

Poster Session 3

10:00 – 11:00

Session 6:  Run Time

11:00 – 12:00

 
Title:  COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors
Authors:       Jingzhao Ou, Viktor K. Prasanna
Organization:  University of Southern California
 
Title:  An Execution Environment for Reconfigurable Computing
Authors:  W. Fu, K. Compton
Organization:  University of Wisconsin at Madison

Session 7:  Arithmetic

1:30 – 3:00

 
Title:  Higher Radix Floating-Point Representations for FPGA-Based Arithmetic
Authors:  Bryan Catanzaro, Brent Nelson
Organization:  Brigham Young University
 
Title:  An Analysis of the Double-Precision Floating-Point FFT on FPGAs
Authors:  K. Scott Hemmert, Keith Underwood
Organization:  Sandia National Laboratories
 
Title:  A Comparision of Floating Point and Logarithmic Number Systems for FPGAs
Authors:  Michael Haselman, Michael Beauchamp, Aaron Wood, Scott Hauck, *Keith Underwood, *K. Scott Hemmert
Organization:  University of Washington, Sandia National Laboratories*
 

Poster Session 4

3:00 – 4:00

Session 8:  Device Architecture

4:00 – 5:00

 
Title:  Terrestrial-Based Radiation: A Cautionary Tale      
Authors:  Heather Quinn, Paul Graham
Organization:  Los Alamos National Laboratory
 
Title:  Automating the Layout of Reconfigurable Subsystems using Circuit Generators
Authors:  Shawn Phillips, Scott Hauck
Organization:  University of Washington
 
 

Wednesday 20 April 2005

Session 9:  Networking

8:30 – 10:00

 
Title:  Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network
Authors:  Young H. Cho, William H. Mangione-Smith
Organization:  UCLA
 
Title:  A Framework For Rule Processing in Reconfigurable Network Systems
Authors:  Michael E. Attig, John W. Lockwood
Organization:  Washington University in St. Louis
 
Title:  A Signature Match Processor Architecture for Network Intrusion Detection
Authors:  Janardham Singaraju, Long Bu, John A. Chandy
Organization:  University of Connecticut

Session 10:  Tools II

10:30 – 11:30

 
Title:  Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation
Authors:  Jose Gabriel F. Coutinho, Jun Jiang, Wayne Luk
Organization:  Imperial College
 
Title:  Modeling and FPGA Implementation of Applications using Parameterized Process Networks with Non-Static Parameters
Authors:  Hristo Nikolov, Todor Stefanov, Ed Deprettere
Organization:  Leiden University