The 10th Annual IEEE Symposium
on
Field-Programmable Custom Computing Machines
FCCM '02
Napa, California
21 - 24 April, 2002
Preliminary Program
Sunday 21 April 2002
7:00pm - 9:00pm
Registration and Reception
Monday 22 April 2002
8:30am - 10:00am
Session 1: Applications I
Chair: Roger Woods, Queen's University, Belfast
Authors: Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk, Jason Pelly
Organization: Imperial College and Sony Broadcast and Professinoal Research Lab
Title: Image Registration of real-time video data using the SONIC reconfigurable computer platform
Authors: K.H. Tsoi, K.H. Lee and P.H.W. Leong
Organization: Chinese University of Hong Kong
Title: A Massively Parallel RC4 Encryption Engine
Authors: T. Mitra, T. Chiush
Organization: National University of Singapore and State University of New York
Title: An FPGA Implementation of Triangle Mesh Decompression
11:00am - 12:00pm
Session 2: Networking I
Chair: Wayne Luk, Imperial College
Authors: G. Brebner
Organization: University of Edinburgh
Title: Single-chip Gigabit Mixed-version IP Router on Virtex-II Pro
Authors: T. Sproull, J. Lockwood, D. Taylor
Organization: Washington University
Title: Control and Configuration Software for a Reconfigurable Networking Hardware Platform
1:30pm - 3:00pm
Session 3: Tools I
Chair: Mark Shand, Compaq
Authors: M. Mishra and S. Goldstein
Organization: Carnegie Mellon University
Title: Peer-to-peer Hardware-software Interfaces for Reconfigurable Fabrics
Authors: O. Mencer
Organization: Lucent
Title: PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
Authors: Heidi Ziegler, Mary Hall, Joonseok Park, Pedro Diniz and Byoungro So
Organization: USC/ISI
Title: Coarse-Grain Pipelining for Multiple FPGA Architectures
4:00pm - 5:00pm
Session 4: Template Matching
Chair: Stephen Smith, Lochran
Authors: S. Hezel, A. Kugel, R. Manner and D. Gavrila
Organization: University of Mannheim and DaimlerChrysler
Title: FPGA-based Template Matching using Distance Transforms
Authors: J. Gause, P.Y.K. Cheung, W. Luk
Organization: Imperial College
Title: Reconfigurable Shape-Adaptive Template Matching Architectures
7:00pm - 10:00pm
Demo night
Tuesday 23 April 2002
8:30am - 10:00am
Session 5: Networking II
Chair: Herman Schmit, Carnegie Mellon University
Authors: R. Franklin, D. Carver and B. Hutchings
Organization: Brigham Young University
Title: Assisting Network Intrusion Detection with Reconfigurable Hardware
Authors: P. Bellos, J. Flidr, T. Lehman, B. Schott and K. Underwood
Organization: USC/ISI and Clemson University
Title: GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing
Authors: G. Memik, S. Memik and W. Mangione-Smith
Organization: University of Califonia, Los Angeles
Title: Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic
11:00am - 12:00pm
Session 6: Architecture I
Chair: Andre' DeHon, CALTECH
Authors: G. Stitt, B. Grattan and F. Vahid
Organization: University of California, Riverside
Title: Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
Authors: H. Schmit, B. Levine and B. Ylvisaker
Organization: Carnegie Mellon University
Title: Queue Machines: Hardware Compilation in Hardware
1:30pm - 3:00pm
Session 7: Applications II
Chair: Duncan Buell, Univ. of South Carolina
Authors: C. Plessl and M. Platzner
Organization: Swiss Federal Institute of Technology (ETH) Zurich
Title: Custom Computing Machines for the Set Covering Problem
Authors: G. Lienhart, A. Kugel and R. Manner
Organization: University of Mannheim
Title: Using Floating Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations
Authors: B.C. Schaffer, S.F. Quigley and A.H.C. Chan
Organization: University of Birmingham
Title: Analysis and Implementation of the Discrete Element Method using a Dedicated Highly Parallel Architecture in Reconfigurable Computing
4:00pm - 5:00pm
Session 8: Architecture II
Chair: Scott Hauck, Univ. of Washington
Authors: Rong Yan and Seth Goldstein
Organization: Carnegie Mellon University
Title: Mobile Memory: Improving memory locality in very large reconfigurable fabrics
Authors: A. DeHon, R. Huang, J. Wawrzynek
Organization: CALTECH and UC, Berkeley
Title: Hardware-Assisted Fast Routing
Wednesday 24 April 2002
8:30am - 10:00am
Session 9: Tools II
Chair: Mike Butts, Cadence
Authors: G. Constantinides, P.Y.K. Cheung, W. Luk
Organization: Imperial College
Title: Optimum Wordlength Allocation
Authors: M. Chang and S. Hauck
Organization: University of Washington
Title: Precis: A Design-Time Precision Analysis Tool
Authors: D. Kulkami, W. Najjar, R. Rinker and F. Kurdahi
Organization: Univ. of Calif, Riverside, Univ. of Idaho, and Univ. of Calif., Irvine
Title: Fast Area Estimation to Support Compiler Optimizations in FPGA-based Reconfigurable Systems
10:30am - 11:30am
Session 10: Image Compression
Chair: Jeffrey Arnold, Adaptive Silicon
Authors: T. Fry, S. Hauck
Organization: University of Washington
Title: Hyperspectral Image Compression on Reconfigurable Platforms
Authors: M. Sima, S. Cotofina, S. Vassiliadis, J. van Eijndhoven, K. Vissers
Organization: Delft University of Technology, Philips Research and TriMedia Technologies
Title: MPEG-compliant Entropy Decoding on FPGA-augmented TriMedia/CPU64
Monday 22 April 2002
10:00am - 11:00am
Poster Session 1
Authors: F. Cardells-Tormo and J. Valls-Coquillat
Organization: Polytechnic University of Valencia
Title: High Performance Quadrature Digital Mixers for FPGAs
Authors: S. Melnikoff, S. Quigley and M. Russel
Organization: University of Birmingham
Title: Discrete and Continuous Speech Recognition on an FPGA
Authors: C. Grassmann, J. Anlauf
Organization: Infineon Technologies and University of Bonn
Title: RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks
Authors: H. ElGindy and Y-L Shue
Organization: University of New South Wales
Title: On sparse matrix vector multiplication with FPGA-based systems
Authors: N. Reis and J. de Sousa
Organization: Technical University of Lisbon
Title: On Implementing a Configware/Software SAT Solver
Authors: M. Necker, D. Contis, D. Schimmel
Organization: Georgia Tech
Title: TCP-Stream reassembly and State Tracking in Hardware
Authors: H. Styles and W. Luk
Organization: Imperial College
Title: Accelerating Radiosity Algorithms using Reconfigurable Platforms
Authors: J. Scalera et. al.
Organization: Virginia Tech
Title: Reconfigurable Object Detection in FLIR Image Sequences
3:00pm - 4:00pm
Poster Session 2
Authors: Greg Nash
Organization: Centar
Title: Automatic Latency Optimal Design of FPGA-based Systolic Arrays
Authors: Theerayod Wiangtong, Peter Cheung and Wayne Luk
Organization: Imperial College
Title: Tabu Search with Intensification Strategy for Functional Partitioning and Scheduling in Hardware-Software Codesign
Authors: Wim Bohm, et. al.
Organization: Colorado State University and University of California, Riverside
Title: Compiling ATR Probing Codes for Execution on FPGA Hardware
Authors: N. Weaver and J. Wawrzynek
Organization: University of California, Berkeley
Title: The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks
Authors: A. Koch and N. Kasprzyk
Organization: Technische Universit"at Braunschweig
Title: Module Generator Driving the Compilation for Adaptive Computing Systems
Authors: T. Rissa, M. Vasilko and J. Niittylahti
Organization: Tampere University of Technology and Bournmouth University
Title: System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems
Authors: M. Ward and N.C. Audsley
Organization: University of York
Title: Hardware Implementation of Programming Languages for Real-Time
Authors: J.M.P. Cardoso and M. Weinhardt
Organization: PACT Informationstechnologie GmbH
Title: Fast and Guaranteed C-Compilation onto the PACT-XPP Reconfigurable Computing Platform
Tuesday 23 April 2002
10:00am - 11:00am
Poster Session 3
Authors: T. Yokota et. al.
Organization: Utsunomiya Univ, Nagoya Univ. and Univ. of Electro-Communications
Title: A Scalable FPGA-based Custom Computing Machine for a Medical Image Processing
Authors: Y. Cho, S. Navab and W. Mangione-Smith
Organization: University of California, Los Angeles
Title: Specialized Hardware for Deep Packet Filtering
Authors: J. Tucker, R. Klenke and Q. Shams
Organization: Virginia Commonwealth University and NASA Langley Research Center
Title: An Embedded Configurable Computer Module
Authors: J. Cook, D. Gottlieb, J. Walstrom, S. Ferrera, C-W. Wang, N. Carter
Organization: University of Illinois
Title: Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor
Authors: J. Walstrom, J. Cook, D. Gottlieb, S. Ferrera, C-W. Wang, N. Carter
Organization: University of Illinois
Title: The Design of the Amalgam Reconfigurable Cluster
Authors: W. Landaker and M. Wirthlin
Organization: BYU
Title: Multitasking Configurable Hardware
3:00pm - 4:00pm
Poster Session 4
Authors: K.H. Tsoi, O.Y.H. Cheung and P.H.W. Leong
Organization: Chinese University of Hong Kong
Title: A Variable-Radix Systolic Montgomery Multiplier
Authors: M.P. Leong and P.H.W. Leong
Organization: Chinese University of Hong Kong
Title: A Variable-Radix Digit-Serial Architecture
Authors: M. Martina, G. Masera, G. Piccinini, F. Vacca, M. Zamboni
Organization: Politecnico di Torino
Title: FPGA Superpipelined DSP Core for 3G Wireless Applications
Authors: Altaf Abdul Gaffar, Wayne Luk, Peter Y.K. Cheung and Nabeel Shirazi
Organization: Imperial College and Xilinx
Title: Automating Customisation of Number Representation
Authors: T. Courtney, R. Turner and R. Woods
Organization: Queens University Belfast
Title: Mapping Multi-Polynomial parallel CRC circuits to Virtex FPGA using embedded MUXes
Authors: E. Raman, L. Chakrapani, K. Sankaranarayanan and R. Parthasarathi
Organization: Indian Institute of Science, Georgia Tech, Univ. of Virginia and Anna Univ.
Title: A Scalable Reconfigurable Architecture For Divisibility Testing Of Variable Long Precision Numbers
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