The 9th Annual IEEE Symposium
on
Field-Programmable Custom Computing Machines
FCCM '01
Rohnert Park, California
29 April - 2 May, 2001
Program
Sunday 29 April 2001
7:00pm - 9:00pm
Registration and Reception
Monday 30 April 2001
8:30am - 10:00am
Session 1: DSP
Authors: A. Nayak et. al.
Organization: Northwestern University
Title: Parallelization of MATLAB Applications for a multi-FPGA System
Authors: S-W. Ong, et. al.
Organization: University of Tennessee
Title: Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
Authors: M.P. Leong, C.T. Jin and P.H.W. Leong
Organization: The Chinese University of Hong Kong
Title: Parameterized Module Generator for an FPGA-Based Electronic Cochlea
10:00am - 11:00am
Coffee break and Poster Session
11:00am - 12:00pm
Session 2: Tools
Authors: J. Cardoso
Organization: University of Algarve, Portugal
Title: Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units
Authors: P. Graham, B. Nelson and B. Hutchings
Organization: Brigham Young University
Title: Instrumenting Bitstreams for Debugging FPGA Circuits
12:00pm - 1:30pm
Lunch break
1:30pm - 3:00pm
Session 3: Arithmetic
Authors: G. Constantinides, P.Y.K. Cheung, W. Luk
Organization: Imperial College
Title: The Multiple Wordlength Paradigm
Authors: Z. Huang and M. Ercegovac
Organization: UCLA
Title: FPGA Implementation of Pipelined On-line Scheme for 3-D Vector Normalization
Authors: R. Parthasarathy et. al.
Organization: Anna University
Title: A Reconfigurable Co processor for Variable Long Precision Arithmetic Using Indian Algorithms
3:00pm - 4:00pm
Coffee break and Poster Session
4:00pm - 5:00pm
Session 4: JBits
Authors: Philip B James-Roxby
Organization: Xilinx
Title: An efficient content-addressable memory implementation using
Authors: S. Singh and P. James-Roxby
Organization: Xilinx
Title: Lava and JBits: From HDL to Bitstream in Seconds
7:00pm - 10:00pm
Buffet and Demo Night
Tuesday 1 May 2001
8:30am - 10:00am
Session 5: Architecture I
Authors: A. Dollas et. al.
Organization: Technical University of Crete
Title: Architecture and Application of PLATO, A Reconfigurable Active Network Platform
Authors: K. Compton and S. Hauck
Organization: Northwestern Univ. and Univ. of Washington
Title: Totem: Custom Reconfigurable Array Generation
Authors: T. Kobori et. al.
Organization: University of Tsukuba
Title: A Cellular Automata System with FPGA
10:00am - 11:00am
Coffee break and Poster Session
11:00am - 12:00pm
Session 6: Fault Tolerance
Authors: M. Alderighi et. al.
Organization: CNR and University of Milan
Title: A Fault-Tolerance Scheme for a MIN-based Multi-Sensor System
Authors: W-J. Huang and E. McCluskey
Organization: Stanford University
Title: Column-Based Precompiled Configuration Techniques for FPGA Fault Tolerance
12:00pm - 1:30pm
Lunch break
1:30pm - 3:00pm
Session 7: Architecture II
Authors: Z. Li and S. Hauck
Organization: University of Washington
Title: Configuration Compression for Virtex FPGAs
Authors: Mihai SIMA et. al.
Organization: Delft University of Technology
Title: An 8x8 IDCT Implementation on an FPGA-augmented TriMedia
Authors: P.H.W. Leong et. al.
Organization: Chinese University of Hong Kong
Title: Pilchard - A Reconfigurable Computing Platform with Memory Slot Interface
3:00pm - 4:00pm
Coffee break and Poster Session
4:00pm - 5:00pm
Session 8: Applications I
Authors: K. Underwood, R. Sass and W. Ligon
Organization: Clemson University
Title: Acceleration of a 2D-FFT on an Adaptable Computing Cluster
Authors: A. Benkrid, D. Crookes, K. Benkrid
Organization: Queens University of Belfast
Title: Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA
Wednesday 2 May 2001
8:30am - 10:00am
Session 9: Image Processing
Authors: S. Hemmert and B. Hutchings
Organization: Brigham Young University
Title: An Application-Specific Compiler for High-Speed Binary Image Morphology
Authors: W. Bohm et. al.
Organization: Colorado State Univ
Title: One-step compilation of image processing applications to FPGAs
Authors: K. Benkrid
Organization: Queen's University of Belfast
Title: High Level Programming for FPGA Based Image and Video Processing using Hardware Skeletons
10:00am - 10:30am
Coffee break
10:30am - 12:00pm
Session 10: Applications II
Authors: R. Sidhu and V. Prasanna
Organization: Univ. of Southern California
Title: Fast Regular Expression Matching using FPGAs
Authors: J. de Sousa, J. da Silva, and M. Abramovici
Organization: Lucent
Title: A Configurable Hardware/Software Approach to SAT Solving
Posters
Authors: X. Tang
Organization: Chameleon Systems
Title: Using Software Pipelining to Hide Memory Latency in Chameleon Reconfigurable Processors
Authors: G. Wigley and D. Kearney
Organization: University of South Australia
Title: The Development of an Operating System for Reconfigurable Computing
Authors: J. Harkin, T.M McGinnity, L.P Maguire
Organization: University of Ulster
Title: Modelling and Optimising Run-time Reconfiguration using Evolutionary Computation
Authors: C. Patterson and S. Guccione
Organization: Xilinx, Inc.
Title: JBits Design Abstractions
Authors: P. Diniz and A. Venkatachar
Organization: USC/ISI
Title: A Synthesis Estimation Interface for Configurable Computing
Authors: T. Maruyama
Organization: University of Tsukuba
Title: An Approach for Automatic Data Allocation in C to HDL Compilers
Authors: S. Sezer
Organization: Queens University of Belfast
Title: System on a FPGA Virtual Concatenation
Authors: T. Kean
Organization: Algotronix, Ltd.
Title: Secure Configuration of a Field Programmable Gate Array
Authors: G. Brebner and I. Kennedy
Organization: University of Edinburgh
Title: Circlets: Circuitry over the Internet
Authors: A. Singhal, A. Somani and A. Tyagi
Organization: Iowa State University
Title: A Reconfigurable Cache Module Architecture
Authors: J. Park and P. Diniz
Organization: USC/ISI
Title: Memory Access Scheduling for FPGA-based Computing Engines
Authors: Y. Ha et. al.
Organization: IMEC
Title: A SW/HW interface API for Java/FPGA Co-Designed Applets
Authors: K. Kornmesser
Organization: University of Mannheim
Title: The FPGA Development System CHDL
Authors: S. Derrien, S. Rajopadhye and S. Sur-Kolay
Organization: IRISA and ISI Calcutta
Title: Combining Instruction and Loop Level Parallelism for FPGAs
Authors: Y. Solihin et. al.
Organization: University of Illinois, Los Alamos National Labs, Intel
Title: Mutable Functional Units and Their Applications on Microprocessors
Authors: K. Mackenzie and A. Johnson
Organization: Georgia Institute of Technology
Title: Rapid Synthesis of Pattern Classification Circuits
Authors: J. Gause
Organization: Imperial College
Title: The Effect of FPGA Granularity on Video Codec Implementations
Authors: S. Cuenca
Organization: University of Alicante
Title: Accelerating statistical texture analysis with an FPGA-DSP hybrid architecture
Authors: W. Mahmoud, R. Haggard and M. Abdelrahman
Organization: Tennessee Technological University
Title: Hardware Implementation of Automated Sensor Self-validation System for Cupola Furnaces
Authors: S. Sudhir, S. Goldstein
Organization: CMU
Title: Configuration Caching and Swapping
Authors: T. Todman and W. Luk
Organization: Imperial College
Title: Reconfigurable Designs for Ray Tracing
Authors: J. Patel and V. Prabhu
Organization: Penn State University
Title: Manufacturing Shop-Floor Supercomputer for Distributed Simulation and Control
Authors: W. Luk and O. Mencer
Organization: Imperial College and Lucent
Title: Pipelined Function Evaluation on FPGAs
Authors: Pawel J. Rajda
Organization: AGH Technical University, Cracow, Poland
Title: Optimization of Logic Use on Stereo Vision Algoritm Example
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