| Monday, April 14, 2008 |
| Paper Session 1 : Programming
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Kiwi: Synthesis of FPGA Circuits from Parallel Programs
David Greaves and Satnam Singh
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Hardware Scripting in Gel
Jonathan Bachrach, Dany Qumsiyeh and Mark Tobenkin -- MIT
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Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
John Curreri, Seth Koehler, Brian Holland and Alan D. George
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| Poster Session 1 |
| Paper Session 2 : Network Applications
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A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Hoang Le, Weirong Jiang and Viktor Prasanna
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A Scalable High Throughput Firewall in FPGA
Gajanan Jedhe, Arun Ramamoorthy and Kuruvilla Varghese
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A Memory-Efficient FPGA-Based Classification Engine
Antonis Nikitakis and Ioannis Papaefstathiou
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| Paper Session 3 : Reconfiguration
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The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration
Shannon Koh and Oliver Diessel
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Autonomous System on a Chip Adaptation Through Partial Runtime Reconfiguration
Matthew French, Erik Anderson and Dong-In Kang
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Scheduling Intervals for Reconfigurable Computing
Wenyin Fu and Katherine Compton
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| Poster Session 2 |
| Paper Session 4 : Discrete Applications
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DSPs, BRAMs and a Pinch of Logic: New recipes for AES on FPGAs
Saar Drimer, Tim Gueneysu and Christof Paar
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High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves
Kimmo J�rvinen and Jorma Skytt�
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An FPGA Implementation of Explicit-State Model Checking
Mary Ellen Fuess, Miriam Leeser and Tim Leonard
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| Tuesday, April 15, 2008 |
| Paper Session 5 : Compilation
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Power and Branch Aware Word-Length Optimization
William Osborne, Jose Coutinho, Wayne Luk and Oskar Mencer
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Simultaneous Retiming and Placement for Pipelined Netlists
Ken Eguro and Scott Hauck
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Map-reduce as a Programming Model for Custom Computing Machines
Jackson H.C. Yeung, C.C. Tsang, K.H. Tsoi, Bill S.H. Kwan, Chris C.C. Cheung, Anthony P.C. Chan and Philip H.W. Leong
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| Poster Session 3 |
| Paper Session 6 : Image Processing
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FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography
Jack Coyne, David Cyganski and R. James Duckworth
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Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study
Jeff Chase, Brent Nelson, John Bodily, Zhaoyi Wei and Dah-Jye Lee
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Multiobjective Optimization of FPGA-Based Medical Image Registration
Omkar Dandekar, William Plishker, Shuvra Bhattacharyya and Raj Shekhar
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| Paper Session 7 : Processor Based Architectures
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Scaling Soft Processor Systems
Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan
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Reconfigurable Work Farms on a Massively Parallel Processor Array
Michael Butts, Brad Budlong, Paul Wasson and Ed White
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Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor
Konstantinos Papadopoulos and Ioannis Papaefstathiou
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| Poster Session 4 |
| Paper Session 8 : High Performance Computing
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Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation
David Barrie Thomas and Wayne Luk
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Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer
David DuBois, Andrew DuBois, Carolyn Connor and Poole Steve
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An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular Dynamics
Martin Herbordt, Francois Kosie and Josh Model
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