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| Field-Programmable Custom Computing Machines |
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IEEE Symposium on Field-Programmable Custom Computing MachinesApril 13 - April 15, 2008
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| Sunday, April 13, 2008 -- Old Union - Ballroom - Room 100 | ||
| 6pm-8pm | Registration, wine/cheese reception Panel Session: Novel Architectures and Systems | |
| Monday, April 14, 2008 -- Frances Arrillaga Alumni Center | ||
| 8:00am | Registration opens | |
| 8:30am-9am | Opening remarks | |
| 9am-10am | Session 1: Programming "Kiwi: Synthesis of FPGA Circuits from Parallel Programs" David Greaves and Satnam Singh -- Cambridge University, Microsoft Research Cambridge "Hardware Scripting in Gel" Jonathan Bachrach, Dany Qumsiyeh and Mark Tobenkin -- MIT "Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing" John Curreri, Seth Koehler, Brian Holland and Alan D. George -- NSF Center for High-Performance Reconfigurable Computing | |
| 10am-11am | Break & Poster Session 1 | |
| 11am-12pm | Session 2: Network Applications "A SRAM-based Architecture for Trie-based IP Lookup Using FPGA" Hoang Le, Weirong Jiang and Viktor Prasanna "A Scalable High Throughput Firewall in FPGA" Gajanan Jedhe, Arun Ramamoorthy and Kuruvilla Varghese -- NetLogic Semiconductor, Cisco Systems (India), Indian Institute of Science "A Memory-Efficient FPGA-Based Classification Engine" Antonis Nikitakis and Ioannis Papaefstathiou -- Technical University of Crete | |
| 12pm-2pm | Lunch | |
| 2pm-3pm | Session 3: Reconfiguration "The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration Shannon Koh and Oliver Diessel -- University of New South Wales, Sydney "Autonomous System on a Chip Adaptation Through Partial Runtime Reconfiguration" Matthew French, Erik Anderson and Dong-In Kang -- Information Science Institute East - University of Southern California "Scheduling Intervals for Reconfigurable Computing" Wenyin Fu and Katherine Compton -- University of Wisconsin | |
| 3pm-4pm | Break and Poster Session 2 | |
| 4pm-5pm | Session 4: Discrete Applications "DSPs, BRAMs and a Pinch of Logic: New recipes for AES on FPGAs" Saar Drimer, Tim Gueneysu and Christof Paar -- University of Cambridge and Ruhr University Bochum "High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves" Kimmo Järvinen and Jorma Skyttä -- Helsinki University of Technology "An FPGA Implementation of Explicit-State Model Checking" Mary Ellen Fuess, Miriam Leeser and Tim Leonard -- Northeastern University, Intel Corporation | |
| 5pm-7pm | Free time | |
| 7pm-10pm | Demo Night | |
| Tuesday, April 15, 2008 -- Frances Arrillaga Alumni Center | ||
| 8:00am | Registration opens | |
| 8:45am-9am | Administrative updates | |
| 9am-10am | Session 5: Compilation "Power and Branch Aware Word-Length Optimization" William Osborne, Jose Coutinho, Wayne Luk and Oskar Mencer -- Imperial College London "Simultaneous Retiming and Placement for Pipelined Netlists" Ken Eguro and Scott Hauck -- University of Washington "Map-reduce as a Programming Model for Custom Computing Machines" Jackson H.C. Yeung, C.C. Tsang, K.H. Tsoi, Bill S.H. Kwan, Chris C.C. Cheung, Anthony P.C. Chan and Philip H.W. Leong -- The Chinese University of Hong Kong | |
| 10am-11am | Break and Poster Session 3 | |
| 11am-12pm | Session 6: Image Processing "FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography" Jack Coyne, David Cyganski and R. James Duckworth -- Worcester Polytechnic Institute "Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study" Jeff Chase, Brent Nelson, John Bodily, Zhaoyi Wei and Dah-Jye Lee -- Brigham Young University "Multiobjective Optimization of FPGA-Based Medical Image Registration" Omkar Dandekar, William Plishker, Shuvra Bhattacharyya and Raj Shekhar -- University of Maryland, Baltimore | |
| 12pm-2pm | Lunch | |
| 2pm-3pm | Session 7: Processor-Based Architectures "Scaling Soft Processor Systems" Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan -- University of Toronto "Reconfigurable Work Farms on a Massively Parallel Processor Array" Michael Butts, Brad Budlong, Paul Wasson and Ed White -- Ambric, Inc. "Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor" Konstantinos Papadopoulos and Ioannis Papaefstathiou -- Technical University of Crete | |
| 3pm-4pm | Break and Poster Session 4 | |
| 4pm-5pm | Session 8: High-Performance Computing "Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation" David Barrie Thomas and Wayne Luk -- Imperial College London "Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer" David DuBois, Andrew DuBois, Carolyn Connor and Poole Steve -- Los Alamos National Laboratory "An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular Dynamics" Martin Herbordt, Francois Kosie and Josh Model -- Boston University | |
| 5pm-5:30pm | Closing remarks and feedback | |