FCCM 2000
April 17-19, 2000
Napa Valley, California
Session 1: Architecture
Chair: Andre' DeHon
Design of a VLIW Compute Accelerator on the Transmogrifier-2
L. Zhang, Q. Wang, and D. Lewis
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems
M. Boyd and T. Lurrabee
Configuration Caching Management Techniques for Reconfigurable Computing
Z. Li, K. Compton, and S. Hauck
Session 2: Compilation I
Chair: Wayne Luk
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, and D. Zaretsky
Stream-Oriented FPGA Computing in the Streams-C High Level Language
M. Gokhale, J. Stone, J. Arnold, and M. Kalinowski
Session 3: Applications I
Chair: Philip Freiden
A Reconfigurable Computing Architecture for Microsensors
S. Scalera, M. Falco, and B. Nelson
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor
K. Leung, K. Ma, W. Wong, and P. Leong
Customizing Graphics Applications: Techniques and Programming Interface
H. Styles and W. Luk
Session 4: Compilation II
Chair: Scott Hauck
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines
P. Diniz and J. Park
A C to HDL Compiler for Pipeline Processing on FPGAs
T. Maruyama and T. Hoshino
Session 5: Cryptographic Applications
Chair: John McHenry
High Performance DES Encryption in VirtexTM FPGAs Using JbitsTM
C. Patterson
A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA
M. Leong 0. Cheung, K. Tsoi, and P. Leong
An Adaptive Cryptographic Engine for IPSec Architectures
A. Dandalis, V. Prasanna, and J. Rolim
Session 6: Programming Tools
Chair: Brad Hutchings
Death of the RLOC?
S. Singh
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
P. James-Roxby and S. Guccione
Session 7: Fault Tolerance
Chair: Philip Kuekes
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
J. Emmert, C. Stroud, B. Skaggs, and M. Abramovici
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities
S-Y. Yu, N. Saxena, and E. McCluskey
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
S. Sinha, P. Kamarchik, and S. Goldstein
Session 8: Wireless Applications
Chair: Tom Kean
Session 8: Wireless Applications Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs
C. Dick, F. Harris, and M. Rice
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems
A. Alsolaim, J. Becker, M. Glesner, and J. Starzyk
Session 9: Applications II
Chair: Mike Butts
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
B. Levine, R. Taylor, and H. Schmit
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine
E. Sotiriades, A. Dollas, and P. Athanas
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
C. Ciressan, E. Sanchez, M. Rajman, and J-C. Chappelier
Session 10: Applications III
Chair: Don Bouldin
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
W-J. Huang, N. Saxena, and E. McCluskey
EVIDENCE: An FPGA-Based System for Photon Event IDENtification and CEntroiding
M. Alderighi, S. D’Angelo, and G. Sechi
Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware
Authors: M. Wirthlin, S. Morrison, P. Graham, and B. Bray
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